Abstract In this research, we intend to develop a sinusoidal VCO with low harmonic distortion. A new sinusoidal VCO is developed with only two OTAs. The number of OTAs is fewer than that previously presented in other papers. The oscillator will be easy to debug and the complexity of the oscillator can be reduced. An AGC control mechanism is applied to the VCO to control the oscillation amplitude and to reduce the harmonic distortion. The oscillation is designed with the frequency around 100MHz and the oscillation amplitude is around 100mV. The simulation results and the problem encountered are discussed.

In this work, the circuit implementation of the front-end for Frequency Domain (FD) Sampling Receiver is presented. Shooting for two different applications, two transconductance amplifiers are designed. A high linear transconductance amplifier with 25 dBm IIP3 is proposed to form the high resolution and high sampling rate FD receiver. The whole system achieves an overall sampling rate of 2 Gs/s and resolution of 10 bits. Another low noise transconductance amplifier exploiting noise cancelling is designed to build up the FD wireless communication receiver, which is an excellent candidate for Software Define Radio (SDR) and Cognitve Radio (CR). The proposed noise cancelling scheme can suppress both thermal noise and flicker noise at the frontend. The system Noise Figure (NF) is improved by 3.28 dB. The two transconductance amplifiers are simulated and fabricated with TI 45nm CMOS technology.

No description available.

<p>The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes.</p><p>This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.</p>

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

Thesis (M.S.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 45-46).

This work deals with methods used in design of low voltage operational amplifiers. It describes some of the most commonly used methods. Properties of these methods are verified by computer simulation of operational transconductance amplifiers that are utilizing them.

Low voltage, low power amplifiers are proposed. One of the operational amplifiers is an Operational Transconductance Amplifier (OTA) with wide input and output swing and constant gm. The second and third amplifiers are high-performance Current Operational amplifiers (COAs). All amplifiers have power supply as low as one threshold voltage plus two overdrive voltage. In this thesis, the supply voltage is 1V. Simulation results show that the OTA has the maximum linear range over 0.7V. The transconductance can be 147£gA/V, the power consumption is 0.133mW. There are two designs of the COA. Simulation results show COA(1) with a current gain of 143. The input impedance is 110£[, the output impedance is 240K£[ and the power consumption is 0.15mW. In the simulation results of the COA(2), the current gain is 110. The DC power dissipation is 0.07mW. The input and output impedance are 95£[ and 500K£[, respectively. All the proposed amplifiers are implemented on a TSMC 0.35£gm 2p4m CMOS process technology and analyzed using HSPICE.

The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes. This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.

The aim of the thesis is to get acquainted with the principle and function of functional generators. Furthermore, with their design using active elements that can be electronically controlled. The design and simulation results are presented in Chapter 4, which also shows schematics of simulated and measured circuits.