Global ETD Search

1	Design and Implementation of Reconfigurable Low-Power Pipelined Booth Multiplier Liang, shish-chang 22 August 2007 (has links) With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data, this paper presents architecture of reconfigurable multiplier without the necessity to completely reconfigure the internal layout of a programmable device. The multiplier employs the Booth algorithm which reduces the partial products to half to implement the sign multiplication. In order to reduce power consumption, the proposed multiplier introduces the clock gating technique to disable the circuit which does not need to be computed. Moreover, the energy-efficient multiplier presented in this thesis can perform multiplication with different data widths to further decrease power dissipation and enhance performance. In this work, we proposed two versions of multipliers. The first version is reconfigurable pipelined Booth multiplier, which can perform one n by n multiplication or two n/2 by n/2 multiplications concurrently. When the multiplier performs n-bit multiplication, it can reduce power consumption by disabling the unnecessary blocks according to the input data. The second version further deploys the truncated functionality to provide different way to make multiplication more energy-efficient. Experiment shows that the proposed multipliers can perform multiplication with less energy and lower power dissipation. It is certain that the more functions the design provides, the more area it will cost. truncated multiplier multiplier reconfigurable pipelined low-power
2	Implementation of Arithmetic Component Generator in 3D Graphics Geometry System Wei, Ping-chung 20 August 2007 (has links) We develop a datapath generator for various arithmetic function units required in the design of the geometry subsystem in the 3D graphics application. The operations considered in the geometry subsystem include coordinate transformations and lighting. The generator will automatically generate efficient designs of function units based on the requirements of area, speed and accuracy. The major function units designed in this thesis are divided into two parts: multiplier-related function units and single-value arithmetic function units. In the generation of multipliers, we consider the design of truncated multipliers to reduce the area cost. In the design of other function evaluators, we consider two table-based methods: piecewise interpolation table-based method and the multipartite table-based method. multipartite 3D graphics and geometry subsystem truncated multiplier function evaluator
3	Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers Zhang Jian, Jun-Hong 10 September 2012 (has links) Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems (D-AMPS), etc. FIR filter achieves the frequency response of system requirement using a series of multiplications and additions. Previous papers on FIR hardware implementations usually focus on reducing area and delay of the multiple constant multiplications (MCM) through common sub-expression elimination (CSE) in the transpose FIR filter structure. In this thesis, we first perform optimization for the quantization of FIR filter coefficients that satisfy the target frequency response. Then suitable encoding methods are adopted to reduce the height of the partial products of the MCM in the direct FIR filter structure. Finally, by jointly considering the errors in the truncated multiplications and additions, we can design the hardware-efficient FIR filter that meets the bit accuracy requirement. Experimental results show that although CSE in the transpose FIR structure can reduce more area in MCM, the direct form takes smaller area in registers. Compared with previous approaches, the proposed FIR implementations with direct form has the minimum area cost. Common Sub-expression Elimination (CSE) Booth recoding error analysis truncated multiplier FIR filter multiple constant multiplication (MCM) VLSI design Canonical Signed Digit (CSD) encoding
4	Calcul flottant haute performance sur circuits reconfigurables / High-performance floating-point computing on reconfigurable circuits Pasca, Bogdan Mihai 21 September 2011 (has links) De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcul reconfigurable. Ce cadre distingue explicitement la fonctionnalité combinatoire d'un opérateur, et la problématique de son pipeline pour une précision, une fréquence et un FPGA cible donnés. Afin de pouvoir utiliser FloPoCo pour concevoir des opérateurs haute performance en virgule flottante, il a fallu d'abord concevoir des blocs de bases optimisés. Nous avons d'abord développé des additionneurs pipelinés autour des lignes de propagation de retenue rapides, puis, à l'aide de techniques de pavages, nous avons conçu de gros multiplieurs, possiblement tronqués, utilisant des petits multiplieurs. L'évaluation de fonctions élémentaires en flottant implique souvent l'évaluation en virgule fixe d'une fonction. Nous présentons un opérateur générique de FloPoCo qui prend en entrée l'expression de la fonction à évaluer, avec ses précisions d'entrée et de sortie, et construit un évaluateur polynomial optimisé de cette fonction. Ce bloc de base a permis de développer des opérateurs en virgule flottante pour la racine carrée et l'exponentielle qui améliorent considérablement l'état de l'art. Nous avons aussi travaillé sur des techniques de compilation avancée pour adapter l'exécution d'un code C aux pipelines flexibles de nos opérateurs. FloPoCo a pu ainsi être utilisé pour implanter sur FPGA des applications complètes. / Due to their potential performance and unmatched flexibility, FPGA-based accelerators are part of more and more high-performance computing systems. However, exploiting this flexibility for accelerating floating-point computations by manually using classical circuit description languages (VHDL or Verilog) is very difficult, and sometimes impossible. This thesis has contributed to the development of the FloPoCo software, a C++ framework for describing flexible FPGA-specific arithmetic operators. This framework explicitly separates the description of the combinatorial functionality of an arithmetic operator, and its pipelining for a given precision, operating frequency and target FPGA.In order to be able to use FloPoCo for designing high performance floating-point operators, we first had to design the optimized basic blocks. We first developed pipelined addition architectures exploiting the fast-carry lines present in modern FPGAs. Next, we focused on multiplication architectures. Using tiling techniques, we proposed novel architectures for large multipliers, but also truncated multipliers, based on the multipliers found in modern FPGA DSP blocks. We also present a generic FloPoCo operator which inputs the expression of a function, its input and output precisions, and builds an optimized polynomial evaluator for the fixed-point evaluation of this function. Using this building block we have designed floating-point operators for the square-root and exponential functions which significantly outperform existing operators. Finally, we also made use of advanced compilation techniques for adapting the execution of a C program to the flexible pipelines of our operators. FPGA Virgule flottante FloPoCo Chemin de données arithmétique Pipeline pour une fréquence donnée Addition pipelinée Additionneur rapide Multiplication Karatsuba-Offman Carré Multiplieur tronqué Multiplication par pavage Virgule fixe Approximation polynomiale Racine carrée flottante Exponentielle flottante Accumulation flottante Schéma d'évaluation de Horner Somme de carrés flottante Synthèse de haut niveau Nid de boucles parfait Multiplication de matrices Jacobi Dilemme du fabricant de table Méthode des différences tabulées Communications pipelinées FPGA Floating-point FloPoCo Arithmetic datapath Frequency-driven pipelining Pipelined addition Short-latency adder Multiplication Karatsuba-Offman Squarer Truncated multiplier Multiplication tiling Fixed-point Polynomial approximation Floating-point square root Floating-point exponential Floating-point accumulation Horner datapath Floating-point sum-of-products High-level synthesis Perfect loop nests Matrix-matrix multiply Jacobi stencil Table maker's dilemma Pipelined communications Pipelined communications

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