<p>QC 20160428</p>

Engineers often view variability as undesirable and seek to minimize it, such as when they employ transistor-matching techniques to improve circuit and system performance. Biology, however, makes no discernible attempt to avoid this variability, which is particularly evident in biological nervous systems whose neurons exhibit marked variability in their cellular properties. In previous studies, this heterogeneity has been shown to have mixed consequences on network rhythmicity, which is essential to locomotion and other oscillatory neural behaviors. The systems that produce and control these stereotyped movements have been optimized to be energy efficient and dependable, and one particularly well-studied rhythmic network is the central pattern generator (CPG), which is capable of generating a coordinated, rhythmic pattern of motor activity in the absence of phasic sensory input. Because they are ubiquitous in biological preparations and reveal a variety of physiological behaviors, these networks provide a platform for studying a critical set of biological control paradigms and inspire research into engineered systems that exploit these underlying principles. We are directing our efforts toward the implementation of applicable technologies and modeling to better understand the combination of these two concepts---the role of heterogeneity in rhythmic networks of neurons. The central engineering theme of our work is to use digital and analog platforms to design and build Hodgkin--Huxley conductance-based neuron models that will be used to implement a half-center oscillator (HCO) model of a CPG. The primary scientific question that we will address is to what extent this heterogeneity affects the rhythmicity of a network of neurons. To do so, we will first analyze the locations, continuities, and sizes of bursting regions using single-neuron models and will then use an FPGA model neuron to study parametric and topological heterogeneity in a fully-connected 36-neuron HCO. We found that heterogeneity can lead to more robust rhythmic networks of neurons, but the type and quantity of heterogeneity and the population-level metric that is used to analyze bursting are critical in determining when this occurs.

Στη παρούσα διδακτορική διατριβή του κ. Χαράλαμπου Μιχαήλ με τίτλο «Βελτιστοποίηση Επαναπροσδιοριζόμενων Αρχιτεκτονικών για Απόδοση και Κατανάλωση Ενέργειας για Κρυπτογραφικές Εφαρμογές και Εφαρμογές Κυριαρχούμενες από Δεδομένα» προτείνονται, αναπτύσσονται και μελετώνται αποδοτικές τεχνικές βελτιστοποίησης της απόδοσης ή/και της κατανάλωσης ενέργειας για κρυπτογραφικές εφαρμογές καθώς και εφαρμογές κυριαρχούμενες από δεδομένα που υλοποιούνται σε ενσωματωμένες πλατφόρμες ειδικού σκοπού. Συνολικά, οι προτεινόμενες τεχνικές μελετήθηκαν για τις διάφορες παραμέτρους που έχουν και συνολικά οδήγησαν στην διαμόρφωση της προτεινόμενης γενικής μεθοδολογίας βελτιστοποίησης των κρυπτογραφικών και λοιπών εφαρμογών κυριαρχούμενων από δεδομένα. Τα θεωρούμενα συστήματα στοχεύουν σε αριθμητικά απαιτητικές εφαρμογές και προέκυψαν εντυπωσιακές βελτιστοποιήσεις ειδικά δε στην απόδοση συγκεκριμένων κρυπτογραφικών εφαρμογών όπως οι συναρτήσεις κατακερματισμού και ανάμειξης (hash functions) και κατά συνέπεια και των αντίστοιχων κρυπτογραφιών μηχανισμών στους οποίους αυτές χρησιμοποιούνται. Πρωταρχικός σχεδιαστικός στόχος είναι η αύξηση της ρυθμαπόδοσης σχεδιάζοντας κρυπτογραφικές εφαρμογές για διακομιστές υπηρεσιών ή γενικότερα εφαρμογές κυριαρχούμενες από δεδομένα. Λαμβάνοντας επίσης υπόψη το γεγονός ότι η κρυπτογραφία αποτελεί σήμερα –πιο πολύ παρά ποτέ- ένα αναγκαίο και αναντικατάστατο συστατικό της ανάπτυξης ηλεκτρονικών υπηρεσιών μέσω διαδικτύου και της εν τέλει μετάβασης της ανθρωπότητας στο νέο οικονομικό μοντέλο της «ηλεκτρονικής οικονομίας» είναι προφανής η σημασία της προτεινόμενης μεθοδολογίας και των αντίστοιχων σχεδιασμών που προκύπτουν. Η ολοκλήρωση των κρυπτογραφικών συστημάτων ασφαλείας σε υλικό είναι σχεδόν αναγκαία για τα ενσωματωμένα συστήματα κρυπτογράφησης. Τα πλεονεκτήματα που έχουμε είναι η υψηλή απόδοση, η μειωμένη κατανάλωση ισχύος με μειονέκτημα το κόστος της ολοκλήρωσης σε υλικό. Νέες τεχνολογίες όπως FPGAs (Field-Programmable Gate Array), επιτρέπουν την πιο εύκολη ολοκλήρωση του αλγορίθμου και την ανανέωση - αντικατάστασή του από νεώτερους-βελτιωμένους. Ήδη τα τελευταίας γενιάς FPGAs τείνουν να έχουν τις ιδιότητες των ASICs (Application-Specific Integrated Circuit) -μειωμένη κατανάλωση ισχύος, υψηλή απόδοση, και ρύθμιση της λειτουργικότητας ανάλογα την εφαρμογή. Ένα άλλο πλεονέκτημα των υλοποιήσεων σε υλικό είναι πως από την φύση τους είναι λιγότερο ευαίσθητο σε επιθέσεις κρυπτανάλυσης ενώ μπορούν ευκολότερα να ενσωματώσουν πολιτικές αντιμετώπισης κρυπταναλυτικών τεχνικών . Ερευνητική Συνεισφορά Ανάπτυξη και μελέτη τεχνικών βελτιστοποίησης που οδηγούν σε σχέδια με πολύ υψηλή ρυθμαπόδοση και περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης για κρυπτογραφικές και υπολογιστικά απαιτητικές εφαρμογές Αναπτύσσονται και αναλύονται όλες οι επιμέρους τεχνικές που αξιολογήθηκαν κατά την εκπόνηση της εν λόγω διδακτορικής διατριβής και χρησιμοποιούνται για την βελτιστοποίηση των σχεδίων σε υλικό. Μελετώνται οι παράμετροι εφαρμογής ανάλογα με την υφή της κάθε τεχνικής και τα τιθέμενα σχεδιαστικά κριτήρια, τα οποία εξαρτώνται από τα επιθυμητά χαρακτηριστικά των σχεδίων σε υλικό καθώς και από τις εν γένει προδιαγραφές τους ανάλογα με τον εκάστοτε σχεδιαστικό στόχο. Ανάπτυξη και μελέτη «πάνω-προς-τα-κάτω» μεθοδολογίας βελτιστοποίησης των σχεδίων που οδηγούν σε πολύ υψηλή ρυθμαπόδοση και περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης για κρυπτογραφικές και υπολογιστικά απαιτητικές εφαρμογές Αναπτύσσεται ολοκληρωμένη και δομημένη συνολική μεθοδολογία βελτιστοποίησης σχεδίων, με βάση τις επιμέρους τεχνικές που παρουσιάστηκαν και αναλύθηκαν, που οδηγεί σε γενική μεθοδολογία η οποία είναι εφαρμόσιμη σε όλες σχεδόν τις συναρτήσεις κατακερματισμού για τις οποίες καταφέρνει να παράγει σχέδια υψηλής απόδοσης με περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης. Ταυτόχρονα, αναλύονται τα θεωρητικώς αναμενόμενα οφέλη από την κάθε επιμέρους τεχνική βελτιστοποίησης καθώς και από την συνολική εφαρμογή της μεθοδολογίας βελτιστοποίησης του σχεδιασμού σε υλικό ανάλογα με την επιλεχθείσα τιμή των παραμέτρων της κάθε εφαρμοζόμενης τεχνικής. Ανάπτυξη σχεδίων σε υλικό πολύ υψηλής βελτιστοποίησης για τις συναρτήσεις κατακερματισμού SHA-1 και SHA-256 Παρουσιάζεται η διαδικασία βελτιστοποίησης του σχεδιασμού σε υλικό των δυο πιο σημαντικών συναρτήσεων κατακερματισμού αναφέροντας σε κάθε περίπτωση τα επιμέρους κέρδη, καθώς και την συνολική βελτίωση που επιτεύχθηκε με την εφαρμογή της προτεινόμενης μεθοδολογίας. Οι δύο συναρτήσεις είναι οι SHA-1 (η πιο δημοφιλής συνάρτηση κατακερματισμού στις σημερινές εφαρμογές) και SHA-256 (που αναμένεται να χρησιμοποιηθεί ευρύτατα στο μέλλον παρέχοντας υψηλότερο επίπεδο ασφάλειας). Υλοποιήσεις σε συγκεκριμένες επαναπροσδιοριζόμενες αρχιτεκτονικές συγκρίνονται με αντίστοιχες που έχουν προταθεί ερευνητικά ή είναι εμπορικά διαθέσιμες, αποδεικνύωντας την υπεροχή των προτεινόμενων σχεδίων. Έτσι προκύπτουν σχέδια πολύ υψηλής ρυθμαπόδοσης (τουλάχιστον 160% βελτιωμένοι σε σχέση με συμβατικές υλοποιήσεις) με περιορισμένο κόστος σε επιφάνεια ολοκλήρωσης (λιγότερο από 10% σε επίπεδο συνολικού κρυπτογραφικού συστήματος στην χειρότερη περίπτωση σε σχέση με συμβατικές υλοποιήσεις), βελτιστοποιώντας τον σχεδιαστικό παράγοντα «απόδοση x επιφάνεια ολοκλήρωσης» σε σχέση με άλλες εμπορικές ή ακαδημαϊκές υλοποιήσεις. / In this Ph.D dissertation, certain design techniques and methodologies, for various hardware platforms, aiming to boost performance of cryptographic modules and data intensive applications are presented. This way we manage to obtain hardware designs with extremely high throughput performing much better that anyone else that has been previously proposed either by academia or industry. Taking in consideration the rapid evolution of e-commerce and the need to secure all kind of electronic transactions, it is obvious that there is a great need to achieve much higher throughputs for certain cryptographic primitives. Especially in IPv6, HMAC etc it is crucial to design hash functions that achieve the highest degree of throughput since hashing is the limiting factor in such security schemes. The proposed methodology achieves to tackle this problem achieving to offer design solutions for hashing cores that can increase their throughput up to 160%. The proposed methodology is generally applicable to all kind of hash functions and this is a main characteristic of its importance. The proposed techniques and methodologies go far beyond from just unrolling the rounds of the algorithm and/or using extended pipelining techniques. It offers an analysis on these techniques while at the same time proposes some new, which all together form a holistic methodology for designing high-throughput hardware implementations for hash functions or other data intensive applications. These designs that can achieve high throughput rates are appropriate for high-end applications that are not constrained in power consumption and chip covered area. The main contributions of this PhD thesis involve: Developing and study of certain optimizing techniques for increasing throughput in cryptographic primitives and data intensive applications Certain design techniques that can take part in a generic methodology for improving hardware performance characteristics are proposed and studied. This study has been conducted in terms of each technique’s parameters and certain design criteria are mentioned in order to choose their values. These design criteria depend on the intended hardware characteristics, specifications and available hardware resources for the cryptographic primitive or data intensive application. Developing and study of top-down methodology for increasing throughput in cryptographic primitives and data intensive applications Techniques that were previously proposed and analyzed are merged in order to form propose a top-down methodology able to boost performance of cryptographic primitives and data intensive applications. Design parameters are studied in order to propose various design options with the default one being achieving the highest degree of throughput maintaining the best throughput/area ratio. The proposed methodology can significantly increase throughput of hardware designs leading theoretically even to 160% increase of throughput with less than 10% cost in integration area for the whole cryptographic system. Highly optimized hardware designs for the two main hash functions: SHA-1 and SHA-256 with high-throughput properties. In this contribution high throughput designs and implementations are proposed concerning the two most widely used hash functions SHA-1 and SHA-256. SHA-1 is currently the most widely deployed hashing function whereas SHA-256 has started to phase out SHA-1 due to security issues that have recently been reported. These two designs also serve as case studies for the application of the proposed methodology aiming to increase throughput in cryptographic modules and data intensive applications. Our implementation does not only increases throughput by a large degree, but it also utilizes limited area resources thus offering an advantageous "throughput x area" product in comparison with other hashing cores implementations, proposed either by academia or industry. The proposed design achieves maximum throughput over 4.7 Gbps for SHA-1 and over 4.4 Gbps for SHA-256 in Xilinx Virtex II platform with minor area penalty comparing to conventional implementations. These synthesis results are only slightly decreased after the place-and-route procedure

SILEX é um ambiente aberto e integrado que busca auxiliar a concepção de CIs. 0 sistema e composto por ferramentas internas (servidoras de recursos) e ferramentas do usuário (clientes de recursos). O usuário interage com o sistema SILEX através de uma interface gráfica baseada em janelas, ativando os recursos de forma padronizada e consistente. Sendo um sistema de CAD, SILEX e formado por um conjunto de módulos (ferramentas) interdependentes. Cada módulo realiza a sua função e transmite seus resultados. O usuário torna-se cliente de um conjunto de processos que concorrentemente responde as suas requisições. A ideia básica esconder do usuário os procedimentos que não estão diretamente ligados ao projeto, como: configuração e forma de interação do usuário com as ferramentas; formato, conversão e local de armazenamento dos dados. A regularidade na utilização é um dos principais objetivo do sistema, tendo em vista as constantes mudanças na forma de integração e utilização das ferramentas. Novos algoritmos, quando disponíveis, são informados aos usuários e estes decidem da inclusão em seus ambientes de trabalho, não necessitando qualquer mudança de código. O projetista de ferramentas e auxiliado no desenvolvimento e integração pois conta com um conjunto de rotinas, normas de codificação e serviços prestados. As rotinas permitem a integração das ferramentas ao ambiente, enquanto que as normas regulam a utilização dos recursos disponíveis. A utilização dos recursos dá-se pelo envio de requisições ao servidor do sistema. Os dados gerados pela interação com as ferramentas estão ligados a um projeto, inicialmente definido e cadastrado. Estes são manipulados por uma ferramenta dedicada, que realiza a leitura, escrita e conversão, liberando as ferramentas do usuário destas tarefas. Centralizados, os dados tem controle de acesso, dependência e versão facilitados. SILEX em sua implementação não se beneficia das facilidades adquiridas com a utilização de um framework comercial, visto que foi totalmente construído sobre uma plataforma Open Windows. O objetivo é inicialmente prover soluções simplificadas e eficazes, que permitam a integração de um conjunto de ferramentas e, subsequentemente, incrementar e expandir a fim de que o SILEX tenha todas as características desejadas e ainda não alcançadas pelos frameworks reportados na bibliografia. / SILEX is an open and integrated system built up to aid the design of integrated circuits. The SILEX System is composed of internal resources and user tools (clients of the resources). The user has at his disposal a graphic interface based on the use of windows, activating tools in an uniform and consistent way. The SILEX CAD system is formed by a set of interdependent modules (tools), each one realizing certain function and transmitting data. The designer is client of a set of processes that answer his/her requests. The main idea of the project is to hide from the final user all tasks which are not directly related to the art of design, like format conversion, data storage and maintenance and user interaction with tools. One of the goals of the system is the regularity in its use, for there is always the need to integrate new tools. The user can suply new algorithms that may be included in the working environment without any change in the SILEX code. The system helps tool designers by suplying them with a set of routines, coding rules and resources. The set of routines allows integration of the tool with the system, while the coding rules normalize the use of the available resources. All data generated by the user interaction with the available tools is linked to a Project, previously defined and cataloged. Data is then handled by a dedicated tool performing I/O, responsible for the reading, writing and converting of data among different tools, freeing User Tools from this task. By being centralized, Project Data are controlled regarding access, dependency and versioning. SILEX is completely built on top of the OpenWindows environment. Its goal is to initially provide simple and efficient solutions that allow the integration of a set of tools. Next tasks will be the enhancement of the system so that SILEX acquires all desirable characteristics not yet reached or reported in the literature.

SILEX é um ambiente aberto e integrado que busca auxiliar a concepção de CIs. 0 sistema e composto por ferramentas internas (servidoras de recursos) e ferramentas do usuário (clientes de recursos). O usuário interage com o sistema SILEX através de uma interface gráfica baseada em janelas, ativando os recursos de forma padronizada e consistente. Sendo um sistema de CAD, SILEX e formado por um conjunto de módulos (ferramentas) interdependentes. Cada módulo realiza a sua função e transmite seus resultados. O usuário torna-se cliente de um conjunto de processos que concorrentemente responde as suas requisições. A ideia básica esconder do usuário os procedimentos que não estão diretamente ligados ao projeto, como: configuração e forma de interação do usuário com as ferramentas; formato, conversão e local de armazenamento dos dados. A regularidade na utilização é um dos principais objetivo do sistema, tendo em vista as constantes mudanças na forma de integração e utilização das ferramentas. Novos algoritmos, quando disponíveis, são informados aos usuários e estes decidem da inclusão em seus ambientes de trabalho, não necessitando qualquer mudança de código. O projetista de ferramentas e auxiliado no desenvolvimento e integração pois conta com um conjunto de rotinas, normas de codificação e serviços prestados. As rotinas permitem a integração das ferramentas ao ambiente, enquanto que as normas regulam a utilização dos recursos disponíveis. A utilização dos recursos dá-se pelo envio de requisições ao servidor do sistema. Os dados gerados pela interação com as ferramentas estão ligados a um projeto, inicialmente definido e cadastrado. Estes são manipulados por uma ferramenta dedicada, que realiza a leitura, escrita e conversão, liberando as ferramentas do usuário destas tarefas. Centralizados, os dados tem controle de acesso, dependência e versão facilitados. SILEX em sua implementação não se beneficia das facilidades adquiridas com a utilização de um framework comercial, visto que foi totalmente construído sobre uma plataforma Open Windows. O objetivo é inicialmente prover soluções simplificadas e eficazes, que permitam a integração de um conjunto de ferramentas e, subsequentemente, incrementar e expandir a fim de que o SILEX tenha todas as características desejadas e ainda não alcançadas pelos frameworks reportados na bibliografia. / SILEX is an open and integrated system built up to aid the design of integrated circuits. The SILEX System is composed of internal resources and user tools (clients of the resources). The user has at his disposal a graphic interface based on the use of windows, activating tools in an uniform and consistent way. The SILEX CAD system is formed by a set of interdependent modules (tools), each one realizing certain function and transmitting data. The designer is client of a set of processes that answer his/her requests. The main idea of the project is to hide from the final user all tasks which are not directly related to the art of design, like format conversion, data storage and maintenance and user interaction with tools. One of the goals of the system is the regularity in its use, for there is always the need to integrate new tools. The user can suply new algorithms that may be included in the working environment without any change in the SILEX code. The system helps tool designers by suplying them with a set of routines, coding rules and resources. The set of routines allows integration of the tool with the system, while the coding rules normalize the use of the available resources. All data generated by the user interaction with the available tools is linked to a Project, previously defined and cataloged. Data is then handled by a dedicated tool performing I/O, responsible for the reading, writing and converting of data among different tools, freeing User Tools from this task. By being centralized, Project Data are controlled regarding access, dependency and versioning. SILEX is completely built on top of the OpenWindows environment. Its goal is to initially provide simple and efficient solutions that allow the integration of a set of tools. Next tasks will be the enhancement of the system so that SILEX acquires all desirable characteristics not yet reached or reported in the literature.

SILEX é um ambiente aberto e integrado que busca auxiliar a concepção de CIs. 0 sistema e composto por ferramentas internas (servidoras de recursos) e ferramentas do usuário (clientes de recursos). O usuário interage com o sistema SILEX através de uma interface gráfica baseada em janelas, ativando os recursos de forma padronizada e consistente. Sendo um sistema de CAD, SILEX e formado por um conjunto de módulos (ferramentas) interdependentes. Cada módulo realiza a sua função e transmite seus resultados. O usuário torna-se cliente de um conjunto de processos que concorrentemente responde as suas requisições. A ideia básica esconder do usuário os procedimentos que não estão diretamente ligados ao projeto, como: configuração e forma de interação do usuário com as ferramentas; formato, conversão e local de armazenamento dos dados. A regularidade na utilização é um dos principais objetivo do sistema, tendo em vista as constantes mudanças na forma de integração e utilização das ferramentas. Novos algoritmos, quando disponíveis, são informados aos usuários e estes decidem da inclusão em seus ambientes de trabalho, não necessitando qualquer mudança de código. O projetista de ferramentas e auxiliado no desenvolvimento e integração pois conta com um conjunto de rotinas, normas de codificação e serviços prestados. As rotinas permitem a integração das ferramentas ao ambiente, enquanto que as normas regulam a utilização dos recursos disponíveis. A utilização dos recursos dá-se pelo envio de requisições ao servidor do sistema. Os dados gerados pela interação com as ferramentas estão ligados a um projeto, inicialmente definido e cadastrado. Estes são manipulados por uma ferramenta dedicada, que realiza a leitura, escrita e conversão, liberando as ferramentas do usuário destas tarefas. Centralizados, os dados tem controle de acesso, dependência e versão facilitados. SILEX em sua implementação não se beneficia das facilidades adquiridas com a utilização de um framework comercial, visto que foi totalmente construído sobre uma plataforma Open Windows. O objetivo é inicialmente prover soluções simplificadas e eficazes, que permitam a integração de um conjunto de ferramentas e, subsequentemente, incrementar e expandir a fim de que o SILEX tenha todas as características desejadas e ainda não alcançadas pelos frameworks reportados na bibliografia. / SILEX is an open and integrated system built up to aid the design of integrated circuits. The SILEX System is composed of internal resources and user tools (clients of the resources). The user has at his disposal a graphic interface based on the use of windows, activating tools in an uniform and consistent way. The SILEX CAD system is formed by a set of interdependent modules (tools), each one realizing certain function and transmitting data. The designer is client of a set of processes that answer his/her requests. The main idea of the project is to hide from the final user all tasks which are not directly related to the art of design, like format conversion, data storage and maintenance and user interaction with tools. One of the goals of the system is the regularity in its use, for there is always the need to integrate new tools. The user can suply new algorithms that may be included in the working environment without any change in the SILEX code. The system helps tool designers by suplying them with a set of routines, coding rules and resources. The set of routines allows integration of the tool with the system, while the coding rules normalize the use of the available resources. All data generated by the user interaction with the available tools is linked to a Project, previously defined and cataloged. Data is then handled by a dedicated tool performing I/O, responsible for the reading, writing and converting of data among different tools, freeing User Tools from this task. By being centralized, Project Data are controlled regarding access, dependency and versioning. SILEX is completely built on top of the OpenWindows environment. Its goal is to initially provide simple and efficient solutions that allow the integration of a set of tools. Next tasks will be the enhancement of the system so that SILEX acquires all desirable characteristics not yet reached or reported in the literature.

Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS VLSI circuits. In this thesis, a new approach is proposed involving dual dielectric of dual thicknesses (DKDT) for the reducing both ON and OFF state gate leakage. It is claimed that the simultaneous utilization of SiON and SiO2 each with multiple thicknesses is a better approach for gate leakage reduction than the conventional usage of a single gate dielectric (SiO2), possibly with multiple thicknesses. An algorithm is developed for DKDT assignment that minimizes the overall leakage for a circuit without compromising with the performance. Extensive experiments were carried out on ISCAS'85 benchmarks using 45nm technology which showed that the proposed approach can reduce the leakage, as much as 98% (in an average 89.5%), without degrading the performance.

The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. In addition we present two new partitioning algorithms both of them taking cones as fundamental units for building partitions.

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