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Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

The security of service, confidential data, and intellectual property are threatened by physical attacks, which usually include reading and tampering the data. In many cases, attackers can have access to the tools and equipment that can be used to read the memory or corrupt it, either by invasive or non-invasive means. The secret keys used by cryptographic algorithms are usually stored in a memory. Physical unclonable functions (PUFs) are promising to deal with such vulnerabilities since, in the case of PUFs, the keys are generated only when required and do not need to be stored on a powered-off chip. PUFs use the inherent variations in the manufacturing process to generate chip-unique output sequences (response) to a query (challenge). These variations are random, device-unique, hard to replicate even by the same manufacturer using identical process, equipment and settings, and supposed to be static, making the PUF an ideal candidate for generation of cryptographic keys. This thesis work focuses on a delay-based PUF called arbiter PUF. It utilizes the intrinsic propagation delay differences of two symmetrical paths. In this work, an arbiter PUF implemented in Altera FPGA has been evaluated. The implementation includes Verilog HDL coding, placement and routing, and the communication methods between PC and FPGAs to make testing more efficient. The experimental results were analyzed based on three criteria, reliability, uniqueness, and uniformity. Experimental results show that the arbiter PUF is reliable with respect to temperature variations, although the bit error rate increases as the temperature difference becomes larger. Results also reveal that the uniqueness of the PUFs on each FPGA device is particularly low but on the other hand, the proportions of different response bits are uniform after symmetric routing is performed. / Tjänstens säkerhet, konfidentiella uppgifter och immateriell egendom hotas av fysiska attacker, som vanligtvis inkluderar läsning och manipulering av uppgifterna. I många fall kan angripare ha tillgång till de verktyg och utrustning som kan användas för att läsa minnet eller skada det , antingen med invasiva eller icke-invasiva medel. De hemliga nycklarna som används av kryptografiska algoritmer lagras vanligtvis i ett minne. Fysiska okonabla funktioner (PUF: er) lovar att hantera sådana sårbarheter eftersom, för PUF: er, nycklarna genereras endast när det behövs och inte behöver lagras på ett avstängd chip. PUF: er använder de inneboende variationerna i tillverkningsprocessen för att generera chip-unika utgångssekvenser (svar) på en fråga (utmaning). Dessa variationer är slumpmässiga, enhetsunika, svårt att kopiera till och med av samma tillverkare med identisk process, utrustning och inställningar, och antas vara statisk, vilket gör PUF till en idealisk kandidat för generering av kryptografiska nycklar. Detta avhandlingsarbete fokuserar på en fördröjningsbaserad PUF som kallas arbiter PUF. Den använder de inneboende utbredningsfördröjningsskillnaderna för två symmetriska vägar. I detta arbete har en arbiter PUF implementerad i Altera FPGA utvärderats. Implementeringen inkluderar Verilog HDLkodning, placering och routing och kommunikationsmetoderna mellan PC och FPGA för att effektivisera testningen. De experimentella resultaten analyserades baserat på tre kriterier, tillförlitlighet, unikhet och enhetlighet. Experimentella resultat visar att arbiter PUF är tillförlitlig med avseende på temperaturvariationer, även om bitfelfrekvensen ökar när temperaturdifferensen blir större. Resultaten avslöjar också att unikheten hos PUF: erna på varje FPGA-enhet är särskilt låg men å andra sidan är proportionerna av olika svarbitar enhetliga efter att symmetrisk dirigering har utförts.

With the rapid growth of Internet-of-Things (IoT), billions of devices are expected to be interconnected to provide various services appealing to users. Many devices will get an access to valuable information which is likely to increase the number of malicious attacks on these devices in the future. Therefore, security is considered as one of the most critical challenges in the development of IoT. In order to secure resource-constrained devices such as sensors or radio frequency identification (RFID) tags which form the backbone of IoT, lightweight cryptographic algorithms are required. This thesis focuses on the problem of message authentication. To authenticate a message means to verify that the message: (1) comes from the right sender (i.e. its authenticity), and (2) has not been modified (i.e. its integrity). It is challenging to use traditional message authentication methods in resource-constrained devices because typically they can allocate only a few hundred gates for implementing security due to their limited computing, storage and energy resources. To address these needs, a new message authentication algorithm based on a Cryptographic Cyclic Redundancy Check (C-CRC) was developed by KTH in collaboration with Ericsson. In this thesis, we implemented C-CRC and compared it with KECCAK Message Authentication Code (KMAC) standardized by the National Institute of Standards and Technology (NIST) in 2016. First, MATLAB and Verilog versions were developed for both algorithms. The comparison of these two versions allowed us to verify the correctness of algorithms functionality. After that, the Verilog descriptions were simulated in ModelSim and synthesized using Synopsys design compiler. Finally, placement and routing was performed using Cadence SoC Encounter. The evaluation results show that C-CRC outperforms KMAC in terms of area, power, throughput per area, and energy per bit. However, C-CRC is worse than KMAC in terms of latency. We have also investigated several different options of implementing C-CRC, including producing more than one bit of output per clock cycle. We found that such a technique improves throughput of C-CRC with the minimal penalty in area and power consumption

Microgrids containing photovoltaic (PV) cells and wind power gain more and more interest. These microgrids may work in stand-alone mode ("islanding") or be conncted to the main grid. In both modes of operation, power quality must be monitored and controlled. This report focuses on microgrids and aims to implement a monitoring system based on FPGA. In the monitoring system, two applications can be achieved, firstly a PAS-MPPT algorithm in a DC-DC boost converter to improve the maximun power point tracking of a PV unit, and secondly a detection and switching system of the grid mode - stand-alone or connected to the main grid. Simulation results prove the Verilog programs in FPGA are suitable to be used in microgrids.