In this thesis, an FPGA based hash processor is designed and implemented using a hardware description language / VHDL. Hash functions are among the most important cryptographic primitives and used in the several fields of communication integrity and signature authentication. These functions are used to obtain a fixed-size fingerprint or hash value of an arbitrary long message. The hash functions SHA-1 and SHA2-256 are examined in order to find the common instructions to implement them using same hardware blocks on the FPGA. As a result of this study, a hash processor supporting SHA-1 and SHA2-256 hashing and having a standard UART serial interface is proposed. The proposed hash processor has 14 instructions. Among these instructions, 6 of them are special instructions developed for SHA-1 and SHA-256 hash functions. The address length of the instructions is six bits. The data length is 32 bits. The proposed instruction set can be extended for other hash algorithms and they can be implemented over the same architecture. The hardware is described in VHDL and verified on Xilinx FPGAs. The advantages and open issues of implementing hash functions using a processor structure are also discussed.

<p>Detta dokument beskriver hur man kan använda kameramodulen TRDB DC2 från Terasic tillsammans med ett utvecklingskort DE2 för Alteras FPGA-kretsar. Kamerabilder överförs från kameramodulen till en VGA-skärm. VGA-bilden har en upplösning på 640 x 480 pixlar och 10bitars upplösning på färgerna. Systemet presterar maximalt 15 bilder per sekund och det är själva bildsensorn som sätter den begränsningen, man kan bla ändra exponeringstid och frysa bilden om man så vill. Hela projektet är skrivet i VHDL och arbetet är gjort i Quartus 6.0 från Altera. VHDL-koden är skriven i första hand för att vara lättförståelig och enkel att modifiera, några större ansträngningar för att minimera hårdvara eller på annat sätt effektivisera konstruktionen har inte gjorts.</p>

Title from PDF of title page. / Document formatted into pages; contains 68 pages. / Thesis (M.S.Cp.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: The main aim of a text-to-speech synthesis system is to convert ordinary text into an acoustic signal that is indistinguishable from human speech. This thesis presents an architecture to implement a concatenative speech synthesis algorithm targeted to FPGAs. Many current text-to-speech systems are based on the concatenation of acoustic units of recorded speech. Current concatenative speech synthesizers are capable of producing highly intelligible speech. However, the quality of speech often suffers from discontinuities between the acoustic units, due to contextual differences. This is the easiest method to produce synthetic speech. It concatenates prerecorded acoustic elements and forms a continuous speech element. The software implementation of the algorithm is performed in C whereas the hardware implementation is done in structural VHDL. A database of acoustic elements is formed first with recording sounds for different phones. / ABSTRACT: The architecture is designed to concatenate acoustic elements corresponding to the phones that form the target word. Target word corresponds to the word that has to be synthesized. This architecture doesn't address the form discontinuities between the acoustic elements as its ultimate goal is the synthesis of speech. The Hardware implementation is verified on a Virtex (v800hq240-4) FPGA device. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.

Thèse de doctorat--Électronique et communications--Paris--ENST, 2004. / Bibliogr. p. 105-109. Résumé en français et en anglais.

Thèse de doctorat : SCIENCES ET TECHNIQUES : Metz : 1999. / 1999METZ021S. 38 ref.

Reproduction de : Thèse de doctorat : Microélectronique : Toulouse, INPT : 2005. / Titre provenant de l'écran-titre. Bibliogr. 126 réf.

Thesis (M.S. in Computer Science)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Neil Rowe. Includes bibliographical references (p. 129-130). Also available online.

Zugl.: Darmstadt, Techn. Univ., Diss., 2009

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Douglas Fouts, Ted Lewis. Includes bibliographical references (p. 125). Also available online.