This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the proposed system. The software system was designed and developed using C++ and OpenCV library on general purpose CPU. The prototype is used to explore and investigate potential segmentation and detection algorithms that might be feasible to design and implement in hardware accelerated environments. These algorithms includes RGB colour conversion, colour segmentation through thresholding, noise reduction through median filter, morphological operations through erosion and dilation, and sign detection through template matching. The second phase, a hardware-based design of the system was developed using the same algorithms used in the software design. The hardware design is composed of 20 image processing components each designed to xxx fully parallelized and pipelined xxx. The hardware implementation was developed using VHDL as the hardware description language targeting a Xilinix Virtex-6 FPGA XC6VLX240T device. The development environment is Xilinx ISE®Design Suite version 14.3. A set of 20 640x480 test images was used as the test data for the verification and testing of this work. The images was captured by a smart-phone camera in various weather and lightning conditions. The software implementation delivered speed limit detection results with a success rate of 75%. The hardware implementation was only simulated using Xilinx ISE Simulator (ISim) with a overall system latency of 12964 clock cycles. According to the Place and Route report the maximum operation frequency for the proposed hardware design is 71,2 MHz. The design only utilized 2% of the slice registers, 4% of the slice Look up Tables (LUT), and 11% of the block memory. This thesis project concludes the work based on the provided software and hardware implementation and performance analysis results. Also the conclusions chapter provides recommendations and future work for possible extension of the project.

This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the proposed system. The software system was designed and developed using C++ and OpenCV library on general purpose CPU. The prototype is used to explore and investigate potential segmentation and detection algorithms that might be feasible to design and implement in hardware accelerated environments. These algorithms includes RGB colour conversion, colour segmentation through thresholding, noise reduction through median filter, morphological operations through erosion and dilation, and sign detection through template matching. The second phase, a hardware-based design of the system was developed using the same algorithms used in the software design. The hardware design is composed of 20 image processing components each designed to xxx fully parallelized and pipelined xxx. The hardware implementation was developed using VHDL as the hardware description language targeting a Xilinix Virtex-6 FPGA XC6VLX240T device. The development environment is Xilinx ISE®Design Suite version 14.3. A set of 20 640x480 test images was used as the test data for the verification and testing of this work. The images was captured by a smart-phone camera in various weather and lightning conditions. The software implementation delivered speed limit detection results with a success rate of 75%. The hardware implementation was only simulated using Xilinx ISE Simulator (ISim) with a overall system latency of 12964 clock cycles. According to the Place and Route report the maximum operation frequency for the proposed hardware design is 71,2 MHz. The design only utilized 2% of the slice registers, 4% of the slice Look up Tables (LUT), and 11% of the block memory. This thesis project concludes the work based on the provided software and hardware implementation and performance analysis results. Also the conclusions chapter provides recommendations and future work for possible extension of the project.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / IRIG-106 Chapter 5 describes a method for encoding voice using a simple circuit to reduce the overall bit rate and still achieve good quality voice. This well described Continuously Variable Slope Delta Modulation (CVSD) circuit can be obtained using analog parts. A more stable implementation of CVSD can be obtained by designing an anti-aliasing input filter, an A/D converter, and logic. This paper describes one implementation of the CVSD using a standard A/D converter and logic.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper describes the development of a Reed-Solomon (RS) Encoder-Decoder which implements the RS segment of the telemetry channel coding scheme recommended by the Consultative Committee on Space Data Systems (CCSDS)[1]. The Euclidean algorithm has been chosen for the decoder implementation, the hardware realization taking a systolic array approach. The fully pipelined decoder runs on a single clock and the operating speed is limited only by the Galois Field (GF) multiplier's delay. The circuit has been synthesised from VHDL descriptions and the hardware is being realised using programmable logic chips. This circuit was simulated for functional operation and found to perform correction of error patterns exactly as predicted by theory.

Approved for public release; distribution is unlimited / Communication is an essential skill for every military officer. Their jobs are accomplished through communication This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. The research builds on previous work which implemented a false radar imaging algorithm on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the SRC-6E provides and effective solution for implementations with greater than 64 range bins. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code is included in the appendices.

The FITkit platform incorporates an embedded system which enables students to create and implement complex designs not only of software projects but also of hardware projects or complete applications. So it is very important to invent and implement methods that can be used for testing the system during its whole life cycle. This thesis is engaged in testing the FITkit. The first part of the thesis is dedicated to familiarizing with the FITkit and its whole architecture. Terminology description and analysis of the dilemmas in testing can be found in the next part of the thesis. Further follows description of methods and procedures for testing the FITkit platform. A part of the thesis is a design of a testing application and description of its practical realization.

Este trabalho visa desenvolver instrumentação de apoio para tratamentos de reabilitação de lesados medulares. Trata de propor um sistema de controle, seus componentes e operações para monitorar o avanço do esgotamento muscular, com o intuito de evitar a fatigamento total da estrutura muscular principalmente se sob efeitos de Estimulação Elétrica Neuro-Muscular (EENM). Foi desenvolvida pesquisa inicial sobre a atividade elétrica de grupos musculares clinicamente normais em contração voluntária e de grupos musculares paralisados sob efeito de eletro-estimulação. Em ambos casos, eletromiogramas de superfície (EMG) foram processados para verificar a manifestação mioelétrica da fadiga. Índices de contração muscular foram selecionados para utilização no sistema de controle da EENM. Serão apresentados os cálculos e rotinas computacionais utilizadas no projeto e simulação do Bloco de processamento digital (BPD), dedicado a monitorar os sinais do sistema de controle da EENM para avaliar o progresso do esgotamento muscular sobre os sinais de EMG, e quantificar o decréscimo da energia muscular em função do tempo em que a estrutura estiver sendo exercitada, contribuindo para monitorar a performance física tanto de indivíduos normais quanto de lesados medulares. / This work aims to develop support instrumentation to be used on Rehabilitation Treatments of medullar injured individuals. It proposes a control system, its components and operations to monitor muscular exhaustion, with the objective to avoid the total muscle structure fatigue mainly under effects of Neural-Muscular Electrical Stimulation (EENM). It was carried out an initial research into the electric activity of clinically normal muscle groups under voluntary contraction and of paralyzed muscles groups under electrical stimulation effects. In both cases, the surface electromyogram signals (EMG) have been processed to verify the myoelectric manifestation of fatigue. Muscular Contraction Indexes were selected to be used in the EENM Control System. It will be presented the calculus and computational routines used in the design and simulation of the Digital Processing Block (BPD), dedicated to monitor the signals of the EENM Control System to evaluate the progress of the muscular exhaustion in EMG signals, and quantify the muscular energy decrease as a function of the time when the structure is exercised, contributing to monitor the physical performance of normal and medullar injured individuals.

La Transformada Rápida de Fourier SplitRadix (SRFFT) es un algoritmo computacionalmente eficiente que se utiliza para calcular la Transformada Discreta de Fourier (DFT), la cual a partir de una secuencia finita de datos, obtiene otra que describe su comportamiento en el dominio de la frecuencia. Esta herramienta se utiliza en óptica, acústica, física cuántica, teorías de sistemas, tratamiento de señales, reconocimiento de voz, entre otros. / Tesis

Al implementar un algoritmo de procesamiento digital de señales en hardware es muy común encontrarse con funciones matemáticas trascendentales las cuales, en principio, se pueden implementar usando la serie de Taylor o diseñando un hardware específico para cada función. A fin de mejorar su rendimiento se desarrolló el algoritmo Coordenado Circular, Hiperbólico y Lineal (CORDIC), el cual reduce tanto el uso de compuertas lógicas como el número de iteraciones empleadas al implementar una función trascendental. / Tesis

El presente trabajo consiste en el diseño de un controlador digital para un estimulador de prótesis epiretinal que está conformada por una cámara, un procesador de video, la caja de componentes electrónicos con el controlador incluido y el arreglo de electrodos. Esta prótesis se implanta quirúrgicamente en el paciente que sufre de enfermedades degenerativas de la retina como Retinitis Pigmentosa y Degeneración Macular relacionada con la edad. Las entradas del controlador serán enviadas por un controlador global y las salidas del controlador a un estimulador que usando un arreglo de micro-electrodos estimularía directamente a las neuronas retinales saludables pasando sobre las células fotorreceptoras dañadas por la enfermedad. La forma de onda, periodo, duración, retraso de cada fase y amplitud son importantes para el correcto estimulo de las células neuronales de la retina, por estas razones se diseñó un controlador flexible basado en el diseño ITBCS13 [1] que es capaz de cambiar parámetros y formas de onda de estimulación [2, 3] de forma independiente por canal. Asimismo la corriente de estimulación debe ser bifásica debido a que reduce las cargas residuales que da˜nan el tejido de la retina, por ende la estimulación tendrá una fase catódica y anódica [4]. El controlador digital genera en cuatro canales las formas de onda Senodial, Gaussiana, Rectangular y Triangular a través de las 8 señales de entrada que recibe del controlador global: req, fase, forma onda, tiempo entre fases, tiempo descarga, amplitud, factor duración y reset. Las salidas del controlador al estimulador de cuatro canales serán las fases anódicas, catódicas y la amplitud de la onda: anódico reg , catódico reg y amplitud reg. El diseño del controlador es basado en bloques digitales, codificados por medio del lenguaje de descripción de hardware VHDL. Para realizar la verificación y validación del funcionamiento de dicha descripción se usó la simulación por medio de Testbench en VHDL, empleándose el software ModelSimAltera de la compañía Mentor Graphics [5]. Para la implementación se empleó un FPGA de la familia Cyclone II (tecnología TSMC’s 90-nm) [6]. La frecuencia de operación del controlador es de 164.69 MHz. / Tesis