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Determining the optimum computer architecture configuration for a specific application or a generic algorithm is a difficult task. The complexity involved in today's computer architectures and systems makes it more difficult and expensive to easily and economically implement and test full functional prototypes of computer architectures. High level VHDL performance modeling of architectures is an efficient way to rapidly prototype and evaluate computer architectures. Determining the architecture configuration is fixed, one would like to know the tolerance and expected performance of individual/critical components and also what would be the best way to map the software tasks onto the processor(s). Trade-offs and engineering compromises can be analyzed and the effects of certain component failures and communication bottle-necks can be studied. A part of the research work done for the RASSP (Rapid Prototyping of Application Specific Signal Processors) project funded by Department of Defense contracts is documented in this thesis. The architectures modeled include a single-processor, single-global-bus system; a four processor, single-global-bus system; a four processor, multiple-local-bus, single-global-bus system; and finally, a four processor multiple-local-bus system interconnected by a crossbar interconnection switch. The hardware models used are mostly legacy/inherited models from an earlier project and they were upgraded, modified and customized to suit the current research needs and requirements. The software tasks that are run on the processors are pieces of the signal and image processing algorithm run on the Synthetic Aperture Radar (SAR). The communication between components/devices is achieved in the form of tokens which are record structures. The output is a trace file which tracks the passage of the tokens through various components of the architecture. The output trace file is post-processed to obtain activity plots and latency plots for individual components of the architecture. / Master of Science

This thesis presents a program developed to implement techniques for troubleshooting digital boards. There are old boards still in service that have no built in testing circuits. This makes troubleshooting them time consuming and difficult. In making this program two questions were posed; "How would a technician normally perform this operation?" and "How can a program help him/her do this better?" Having experience as a technician himself, the author could easily answer the first question. The experienced technician would put a known sequence of inputs into the board and compare the actual outputs to the expected. Any outputs that did not compare would lead the technician to the section of board most closely related to the fault. Within this new section, new signals are probed while the same patterns of inputs are repeated. This technique is commonly referred to as bracketing. Bracketing involves these four steps: 1.Select where to probe. 2.Run test inputs and sample. 3.Use sampled information to reduce the suspect set. 4.If the suspect set is not a single component then repeat steps 1 through 4. The answer to the second question has no easy answer. That is where it is hoped this program can help. The program uses information from a non-faulted VHDL model of the board to learn what to expect. Since there is no interface to a real probed board, VHDL is also used to model the faulted board. / Master of Science

This dissertation presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. <b>P-Algorithm</b> is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. <b>E-Algorithm</b> is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation. / Ph. D.

The exponential growth of the World Wide Web (WWW) on the Internet and accompanying WWW browsers has promoted opportunities for new methods of teaching and learning. Teaching does not simply involve presenting textual information over the Internet along with a few hyperlinks, but requires effective user engagement with the teaching module. This is the main challenge in website design. The objective of this thesis is the development of an effective training module made available over the Internet so as to train acquisition and maintenance personnel on how they can use VHDL to design and maintain digital systems. The educational modules provide extensive information on VHDL modeling and testing styles and standards at various abstraction levels. The Sobel edge detector model was chosen as an example to explain the various concepts of modeling and testing. This model was chosen since it was thought to be simple enough for any student to understand, yet complex enough to explain most of the VHDL concepts of modeling and testing. The course material on test bench development at various levels of abstraction, reuse of test bench models, use of configurations for simulation of mixed abstraction and mixed data type models, testing techniques and WAVES was developed as a part of the current thesis. Finally a complete section on website design has been included which explains the design strategy adopted for developing the website and the various key issues involved in presenting teaching modules over the Internet. / Master of Science

Denna rapport omfattar ett 15 poängs (22,5 högskolepoäng) examensarbete vid Karlstads universitet. Arbetet har utförts på plats hos BAE Systems Bofors i Karlskoga. Företaget ville kunna styra en radiostyrd leksaksstridsvagn med en laserpekare. En kamera ansluten till en digital signalprocessor (DSP) skulle kunna detektera var en laserpunkt befinner sig och styra stridsvagnen mot den. Ett styrgränssnitt mellan DSP:n och leksaksstridsvagnen konstruerades och byggdes med hjälp av en programmerbar logisk krets. Leksaksstridsvagnens interna signalsystem analyserades. En manchesterkodad signal i form av ett 32-bitars seriellt kodord hittades, vilket ursprungligen kom från radiostyrningen. Ett styrgränssnitt konstruerades kring en CPLD (Complex Programmable Logic Device) vilken programmerades med VHDL (Very high speed integrated Hardware Description Language) som återskapar den Manchesterkodade styrsignalen. Gränssnittet ansluter till DSP:n som kontrollerar stridsvagnens styrning och övriga funktioner till fullo. Kommunikationen mellan styrgränssnittet och DSP:n sker via ett parallellgränssnitt som är 16-bitar brett. 13 bitar är datasignaler och övriga tre är ”styrbitar” som konfigurerar gränssnittet. En applikation integrerades i projektet för att demonstrera styrgränssnittets funktion. DSP:n tolkar var en laserpunkt befinner sig inom ett kameraområde och skickar motsvarande styrsignaler till leksaksstridsvagnen. / This report consists of a 15 points (22.5 ECTS) Exam Degree project at Karlstad University. The work was done on location at BAE Systems Bofors AB in Karlskoga. The company wanted to control a radio controlled toy tank from a digital signal processor (DSP). A camera connected to the DSP locates the laser point and steers the toy tank towards it. An interface using a programmable logic device was constructed that connects the DSP to the toy tank. The internal signals in the toy tank was analyzed and a Manchester coded signal in form of a 32-bit serial code word was detected. The code word originated from the radio controller. The control interface was built around a CPLD (Complex Programmable Logic Device) which was programmed in VHDL (Very high speed integrated Hardware Description Language). The control interface recreates the signal controlling the toy tank. The interface connects the toy tank to the DSP which controls the toy tank and it’s functions to the full extent. Communication between the interface and the DSP is done via a 16 bit parallel connection. 13 of the bits are data bits and the remaining 3 are control bits that are used to set up the interface. An application was integrated in the project where the DSP is detecting a laser point. Corresponding signals to the laser points position where sent to the control interface to demonstrate the function of the interface.