High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.

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This work lays out the development of a reconfigurable electronic system, which is composed of biologically relevant circuits. This system has been termed a Field-Programmable Neuron Array (FPNA) and is analogous to the more familiar Field-Programmable Gate Array (FPGA) and Field-Programmable Analog Array (FPAA). At the core of the system is an array of output somas based on previously developed bio-physically based channel models. Linking them together is a complex 2D dendrite matrix, FPAA-like floating-gate routing, and associated support circuitry. Several levels of generality give this system unprecedented re-configurability. The dendrite matrix can be arbitrarily configured so that many different topologies of dendrites can be investigated. Different soma circuits can be connected / disconnected to / from the dendrite matrix. Outputs from the somas can be arbitrarily routed to input synapses that exist at each dendrite node as well as the soma nodes. Lastly, the dynamics of each node consist of a mixture of individually tunable parts and global biases. All of this can be configured in concert to investigate neural circuits that exist in biological systems. This chip will have a significant impact on research in many fields including neuroscience, neuromorphic engineering, and robotics. This chip will allow for rapid prototyping of spinal circuits. Since the fundamental circuits of the system are chosen to be biologically relevant, outputs from the various nodes should also be relevant, thus yielding itself to use by neuroscientists. This system also provides a tool by where biological systems can be emulated in real-world electronic systems. Solutions to many problems faced by roboticists (such as bi-pedal standing / walking / running / jumping / climbing and the transitions between states) are present in biology. By providing a chip that can duplicate the same neural circuits that are responsible for these processes in the biology, the hypothesis is that researchers can begin to solve some of the same types of problems in artificial systems.

No description available.

Marroquin and Ramirez (1990) have recently discovered a class of discrete stochastic cellular automata with Gibbsian invariant measures that have a non-reversible dynamic behavior. Practical applications include more powerful algorithms than the Metropolis algorithm to compute MRF models. In this paper we describe a large class of stochastic dynamical systems that has a Gibbs asymptotic distribution but does not satisfy reversibility. We characterize sufficient properties of a sub-class of stochastic differential equations in terms of the associated Fokker-Planck equation for the existence of an asymptotic probability distribution in the system of coordinates which is given. Practical implications include VLSI analog circuits to compute coupled MRF models.

This thesis proposes a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as phase locked loops (PLL), analog to digital convertors (ADC) and input/output (I/O) circuits. I propose to verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Furthermore, I clearly distinguish between the behavioral and electrical domains and define mapping functions between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a sequential quadratic programming (SQP) based optimizer with commercial circuit simulation tools, such as CADENCE SPECTRE. The proposed methodology is then applied for equivalence checking of a PLL as a test case and results are shown which prove the correctness of the proposed methodology.

Power management has had an ever increasing role in the present electronic industry. Battery powered and handheld applications require power management techniques to extend the life of the battery and consequently the operation life of the device. Most systems incorporate several voltage regulators which supply various subsystems and provide isolation among such subsystems. Low dropout (LDO) voltage regulators are generally used to supply low voltage, low noise analog circuitry. Each LDO regulator demands a large external capacitor, in the range of a few microfarads, to perform. These external capacitors occupy valuable board space, increase the IC pin count, and prohibit system-on-chip (SoC) solutions. The presented research provides a solution to the present bulky external capacitor LDO voltage regulators with a capacitor-less LDO architecture. The large external capacitor was completely removed and replaced with a reasonable 100pF internal output capacitor, allowing for greater power system integration for SoC applications. A new compensation scheme is presented that provides both a fast transient response and full range ac stability from a 0mA to 50mA load current. A 50mA, 2.8V, capacitor-less LDO voltage regulator was fabricated in a TSMC 0.35um CMOS technology, consuming only 65uA of ground current with a dropout voltage of 200mV. Experimental results show that the proposed capacitor-less LDO voltage regulator exceeds the current published works in both transient response and ac stability. The architecture is also less sensitive to process variation and loading conditions. Thus, the presented capacitor-less LDO voltage regulator is suitable for SoC solutions.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper describes the design and calibration of a four-channel, airborne, swept-tuned spectrum analyzer used in two hypersonic flight experiments for characterizing dynamic data up to 25 kHz. Built mainly from commercially available analog function modules, the analyzer proved useful for an application with limited telemetry bandwidth, physical weight and volume, and electrical power. The authors discuss considerations that affect the frequency and amplitude calibrations, limitations of the design, and example flight data.

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level.

Neste trabalho é apresentado o projeto de uma fonte de tensão de referência, um circuito capaz de prover uma tensão invariante com a temperatura, a tensão de alimentação e o processo de fabricação. São apresentadas: as equações de funcionamento, os passos para a elaboração da uma topologia final, o dimensionamento dos parâmetros de projeto com o uso de algoritmos metaheurísticos, o desenho do layout e os resultados e análises finais. O projeto emprega a tecnologia CMOS de 0,35 &#956m com quatro camadas de metal da Austria Micro Systems, em que os VTH0\'s dos transistores NMOS e PMOS, modelo típico, são, respectivamente, 0,5 V e -0,7 V. O circuito de fonte de referência é do tipo bandgap e faz a soma ponderada de correntes proporcionais a temperatura para atingir uma tensão de referência. Obteve-se um circuito típico com 0,5 V de tensão de referência, coeficiente de temperatura de 15 ppm/ºC em intervalo de temperatura de -10 a 90ºC em 1,0 V de tensão de alimentação, regulação de linha de 263 ppm/V em um intervalo de variação de 1,0 V a 2,5 V em 27ºC, 2,7 &#956A de corrente consumida e área de 0,11 mm². A introdução de um bloco de ajuste de coeficiente de temperatura, com ajuste digital, permite que mais que 90% dos circuitos produzidos tenham um coeficiente de temperatura de até 30 ppm/ºC. As medidas realizadas no trabalho são provenientes de simulações elétricas realizadas com o ELDO e modelos BSIM3v3. / In this work is presented a design of a reference voltage source, circuits capable to provide an invariant voltage regardless of the temperature, power supply and fabrication process. It\'s presented: the operation equations, the steps to elaborate a final topology, the project parameter sizing using a metaheuristic algorithm, the drawing of the layout, and the final results and its analysis. The design employs an AMS-CMOS 0.35 &#956m technology with four metal levels, whose NMOS and PMOS VTH0\'s for a typical circuit is 0.5 V and -0.7 V. The reference voltage circuit is bandgap and performs a weighted summation of proportional temperature currents to achieve the voltage reference. A typical circuit was obtained with 0.5 V reference voltage, 15 ppm/ºC temperature coefficient in the temperature range of -10 to 90ºC under 1.0 V power supply, 263 ppm/V line regulation in the range of 1.0 V to 2.5 V under 27ºC, 2.7 &#956A power consumption in a 0.11 mm² area. For a projected circuit its also possible to ensure a temperate coefficient under 30 ppm/ºC, for more than 95% of the produced circuits, employing an adjustment block which ought to be digitally calibrated for each circuit.