[pt] Esta dissertação propõe uma nova plataforma reconfigurável analógica destinada à síntese de circuitos analógicos utilizando Algoritmos Genéticos. Plataformas Reconfiguráveis pretendem estabelecer uma nova tendência na síntese de circuitos eletrônicos, digitais ou analógicos. Grande interesse é mostrado por parte dos pesquisadores em relação às características de auto-reconfiguração e auto-adaptação presentes nestas plataformas. Estas são características essenciais aos sistemas que precisam funcionar por muito tempo em ambientes hostis, como por exemplo nas missões de exploração espacial. Industrialmente, estas características são desejáveis na produção de equipamentos em chips reconfiguráveis, a fim de diminuir a taxa de equipamentos descartados por estarem fora das especificações, já que neste caso ele seria reconfigurado. Finalmente, de maneira genérica, estas características de auto-reconfiguração e auto-adaptação da plataforma permitem que circuitos sejam sintetizados, otimizados ou reparados através de métodos evolutivos. O desenvolvimento desta dissertação foi realizado em 4 etapas: pesquisa bibliográfica, especificação e implementação da plataforma e estudo de casos. Na primeira etapa buscou-se estudar a área de Eletrônica Evolutiva, verificando suas maiores conquistas e necessidades. Foi dada ênfase à síntese de circuitos analógicos por evolução extrínseca e consequentemente às plataformas reconfiguráveis analógicas desenvolvidas comercialmente e em laboratórios de pesquisa. A especificação e implementação da plataforma por sua vez ocorreu em três fases ou versões, estando envolvidos o projeto conceitual, a implementação e a obtenção e análise dos resultados em cada uma delas. Na primeira versão buscou- se consolidar o projeto inicial, puramente teórico, implementando um protótipo limitado, que pudesse comprovar a capacidade de reconfiguração e evolução e também as desejáveis características de robustez e transparência. Na segunda versão, implementou-se um Circuito Reconfigurável Analógico maior, permitindo que um número maior de blocos construtores fosse conectado à plataforma, consequentemente permitindo que uma variedade maior de circuitos fosse sintetizada. Na terceira versão, com a técnica estudada e devidamente comprovada pelas versões anteriores, buscou-se melhorar o desempenho da plataforma, implementando uma nova interface entre o Circuito Reconfigurável Analógico e o Algoritmo Genético. Realizou- se um estudo de casos em cada uma das versões descritas acima, objetivando comprovar as características e limitações da plataforma proposta. Na primeira versão, diferentes configurações de inversores foram sintetizadas. Na segunda versão sintetizou-se um ou-exclusivo, que serviu como base de comparação de desempenho com a terceira versão. Nesta última versão sintetizou-se um ou-exclusivo, um multiplexador, um amplificador e um amplificador controlado por tensão. Em relação à síntese, os circuitos sintetizados possuem configurações não convencionais, comprovando a capacidade da técnica de explorar características da física do silício. Além disso, os resultados mostram que a plataforma proposta possui as características desejáveis de uma FPAA, tais como robustez, transparência, flexibilidade e a capacidade de auto- reconfiguração. / [en] This dissertation investigates a new analog reconfigurable platform, developed to supply an environment to evolve generic analog circuits based on discrete components, without the need of simulators. Automatic reconfiguration of programmable devices may potentially be driven by Evolutionary Computation techniques such as Genetic Algorithms. Reconfigurable Platforms promise to establish a new trend in electronic design, where a single device now has the flexibility to implement a wide range of electronic circuits, analog or digital. A major interest is shown by researches towards those platforms characteristics of self- adaptation and self- repairing through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Industrially, those features can be applied on analog Evolvable Hardware chip, with the aim to improve the yield rate and produce smaller circuits. This research had four steps: a study of related works, the concept of the platform, it`s implementation and cases studies. In the first step, the focus was to study about Evolvable Hardware, it`s main researches and published work, eferences, and the area actual position. An emphasis has been given to intrinsic evolution, and consequently, to the study of the analog reconfigurable platforms. The concept of the platform and it`s implementation had three steps, and each one of these had its own concept, implementation and experiments steps. The first step aimed at proving the initial concept, totally theoretical. Due to that a limited prototype has been implemented, and the features of self- adaptation through automatic reconfiguration, tranparency and robustness were studied. In the second step, a bigger Reconfigurable Analog Circuit has been developed, allowing the evolution of a wider range of circuits. In the third step, the initial concept of the plataform was already well proved, so the aim was at developing a better interface between the software and the reconfigurable platform to make the evolution faster. In each one of the steps described above a case study has been done. The focus was to study and prove the platform`s characteristics and drawbacks. The experiments taken in the first step were inverter circuit topologies. In the second step an exclusive-or has been synthetized. The evolution time of this experiment was compared to the evolution time of the same experiment evolved in the third step of implementation of the platform. And in this third step, due to the faster interface, other experiments were evolved, such as a multiplexer circuit and an amplifier. The evolved circuits has shown no conventional designs, proving that the evolutionary algorithms can explore some of the regions beyond the scope of conventional me thods, raising the possibility that better designs can be found. The results have also shown that the proposed platform has the desired features of self-adaptation and self-repairing through automatic reconfiguration, transparency, flexibility and robustness. / [es] Esta disertación propone una nueva plataforma analógica reconfigurable destinada a la síntesis de circuitos analógicos utilizando Algoritmos Genéticos. Las Plataformas Reconfigurables pretenden establecer una nueva tendencia en la síntesis de circuitos electrónicos, digitales o analógicos. Existe gran interés por parte de los investigadores en relación a las características de autoreconfiguración y autoadaptación presentes en estas plataformas. Estas características son esenciales en sistemas que necesitan funcionar por mucho tiempo en ambientes hostiles, como por ejemplo en las misiones de exploración espacial. Industrialmente, estas características son deseables en la producción de equipos en chips reconfigurables, A fin de disminuir la tasa de equipos descartados por estar fuera de las especificaciones, ya que en este caso él sería reconfigurado. Finalmente, de manera genérica, estas características de autoreconfiguración y autoadaptación de la plataforma permiten que la sintetización de los circuitos, otimizados o reparados a través de métodos evolutivos. Esta disertación fue realizada en 4 etapas: investigación bibliografía, especificación e implementación de la plataforma y estudio de casos. En la primera etapa se desarrolla un estudio sobre temas de Electrónica Evolutiva, que contempla las mayores conquistas y necesidades de ésta área. Se enfatizó en la síntesis de circuitos analógicos por evolución extrínseca y como consecuencia en las plataformas reconfigurables analógicas desarrolladas comercialmente y en laboratórios de investigación. La especificación e implementación de la plataforma por su vez ocurrió en tres fases o versiones, que involucra el proyecto conceptual, la implementación, obtención y análisis de los resultados en cada una de ellas. En la primera versión se consolida el proyecto inicial, puramente teórico, implementando un prototipo limitado, que pudiese comprobar la capacidad de reconfiguración y evolución y también las características deseables de robustez y transparencia. En la segunda versión, se implementó un Circuito Reconfigurable Analógico mayor, permitiendo conectar un número mayor de bloques constructores, permitiendo así que una variedad mayor de circuitos fuese sintetizada. En la tercera versión, con la técnica estudiada y comprobada por las versiones anteriores, se buscó mejorar el desempeño de la plataforma, implementando uma nueva interfaz entre el Circuito Reconfigurable Analógico y el Algoritmo Genético. Se realizó un estudio de casos en cada una de las versiones descritas acima, con el objetivo de comprobar las características y limitaciones de la plataforma propuesta. En la primera versión, diferentes configuraciones de inversores fueron sintetizadas. En la segunda versión se sintetizó un o-exclusivo, que sirvió como base de comparación del desempeño con la tercera versión. En esta última versión se sintetizó un o-exclusivo, un multiplexador, un amplificador y un amplificador controlado por tensión. En relación a la síntesis, los circuitos sintetizados poseen configuraciones no convencionales, comprobando la capacidad de la técnica de explorar características de la física del silício. Además, los resultados muestran que la plataforma propuesta posee las características deseables de una FPAA, tales como robustez, transparencia, flexibilidad y la capacidad de auto reconfiguración.

The presented dissertation thesis deals with modular design of analog circuits in CMOS technology. The goal of the work is to design a set of modular microelectronic building blocks and realize the selected modern active circuits, working primarily in current mode. Nevertheless, the modular approach can be used for design of generally known classical elements, e.g. opamps, as well. As a part of the work, the development of the totally new highly versatile active circuit CCTA has been done, including detailed analysis of utilization and introduction of the most interesting applications. This circuit CCTA, together with relative, already theoretically treated circuit CDTA, has been realized here for the first time, in two different topologies. Final circuits were tested. On the basis of measurement results the library of behavioral models for PSpice was created, including exemplary simulations of the selected applications. Based on the obtained knowledge the brief comparison of voltage mode circuits and current mode circuits was done.

No description available.

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients.Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació.Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge.En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius. / Testing circuits is a stage of the production process that is becoming more and more important when a new product is developed. Test and diagnosis techniques for digital circuits have been successfully developed and automated. But, this is not yet the case for analog circuits. Even though there are plenty of methods proposed for diagnosing analog electronic circuits, the most popular are the fault dictionary techniques. In this thesis some of these methods, showing their advantages and drawbacks, are analyzed.During these last decades automating fault diagnosis using Artificial Intelligence techniques has become an important research field. This thesis develops two of these techniques in order to fill in some gaps in fault dictionaries techniques. The first proposal is to build a fuzzy system as an identification tool. The results obtained are quite good, since the faulty component is located in a high percentage of the given cases. On the other hand, the percentage of successes when determining the component's exact deviation is far from being good.As fault dictionaries can be seen as a simplified approach to Case-Based Reasoning, the second proposal extends the fault dictionary towards a Case Based Reasoning system. The purpose isnot to give a general solution, but to contribute with a new methodology. This second proposal improves a fault dictionary diagnosis by means of adding and adapting new cases to develop aCase Based Reasoning system. The case base memory, retrieval, reuse, revise and retain tasks are described. Special attention to the learning process is taken.Several circuits are used to show examples of the test methods described throughout the text. But, in particular, the biquadratic filter is used to test the proposed methodology because it isdefined as one of the benchmarks in the analog electronic diagnosis domain. The faults considered are parametric, permanent, independent and simple, although the methodology can be extrapolated to catastrophic and multiple fault diagnosis. The method is only focused and tested on passive faulty components, but it can be extended to cover active devices as well.

Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 AdautoLT.pdf: 2061017 bytes, checksum: 12a139ba25174e3b22d08cf31c934500 (MD5) Previous issue date: 2009-09-04 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / This work proposes a new methodology to verify those analog circuits, providing an automated tools to help the verifiers to have a more truthful result. This work presents the development of new methodology for analog circuits verification. The main goal is to provide a more automated verification process to certify analog circuits functional behavior. The proposed methodology is based on the golden model technique. A verification environment based on this methodology was built and results of a study case based on the validation of an operational amplifier design are offered as a confirmation of its effectiveness. The results had shown that the verification process was more truthful because of the automation provided by the tool developed / O presente trabalho tem como objetivo desenvolver uma ferramenta de verifica??o para circuitos anal?gicos. O principal objetivo desta ? aumentar a automa??o dos processos de verifica??o. Al?m disso, proporcionar a constru??o de um ambiente de verifica??o capaz de gerar relat?rios ao longo deste processo. Esta metodologia ? baseada na t?cnica do Modelo de Ouro, no entanto, ela tamb?m prop?e uma segunda t?cnica para verificar o modelo de refer?ncia, para se obter resultados mais confi?veis. A metodologia foi utilizada, como estudo de caso, na verifica??o de um amplificador operacional

Goal of this doctoral thesis is to focus to understand of behavior of working of basic electronics circuits and to appoint which parameters of these circuits is possible to control using external digital system. Further the examples of some digitally controlled analog circuits are present and the analysis of these circuits is achieved. Some of these blocks are realized and the results of that’s measuring is presented.

La Non-Linéarité-Différentielle (NLD) et la Non-Linéarité-Intégrale (NLI) sont les performances statiques les plus importantes des Convertisseurs Analogique-Numérique (CAN) qui sont mesurées lors d’un test de production. Ces deux performances indiquent la déviation de la fonction de transfert du CAN par rapport au cas idéal. Elles sont obtenues en appliquant une rampe ou une sinusoïde lente au CAN et en calculant le nombre d’occurrences de chacun des codes du CAN.Ceci permet la construction de l’histogramme qui permet l’extraction de la NLD et la NLI. Cette approche requiert lacollection d’une quantité importante de données puisque chacun des codes doit être traversé plusieurs fois afin de moyenner le bruit et la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. En effet,malgré que les circuits analogiques et mixtes occupent une surface qui n’excède pas généralement 5% de la surface globald’un System-on-Chip (SoC), leur temps de test représente souvent plus que 30% du temps de test global. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d’attention et qui est en train deprendre de l’ampleur. Les CAN de type pipeline offrent un bon compromis entre la vitesse, la résolution et la consommation.Ils sont convenables pour une variété d’applications et sont typiquement utilisés dans les SoCs destinés à des applicationsvidéo. En raison de leur façon particulière du traitement du signal d’entrée, les CAN de type pipeline ont des codes de sortiequi ont la même largeur. Par conséquent, au lieu de considérer tous les codes lors du test, il est possible de se limiter à un sous-ensemble, ce qui permet de réduire considérablement le temps de test. Dans ce travail, une technique pour l’applicationdu test à code réduit pour les CANs de type pipeline est proposée. Elle exploite principalement deux propriétés de ce type deCAN et permet d’obtenir une très bonne estimation des performances statiques. La technique est validée expérimentalementsur un CAN 11-bit, 55nm de STMicroelectronics, obtenant une estimation de la NLD et de la NLI pratiquement identiques àla NLD et la NLI obtenues par la méthode classique d’histogramme, en utilisant la mesure de seulement 6% des codes. / Differential Non Linearity (DNL) and Integral Non Linearity (INL) are the two main static performances ofAnalog to-Digital Converters (ADCs) typically measured during production testing. These two performances reflect thedeviation of the transfer curve of the ADC from its ideal form. In a classic testing scheme, a saturated sine-wave or ramp isapplied to the ADC and the number of occurrences of each code is obtained to construct the histogram from which DNL andINL can be readily calculated. This standard approach requires the collection of a large volume of data because each codeneeds to be traversed many times to average noise. Furthermore, the volume of data increases exponentially with theresolution of the ADC under test. According to recently published data, testing the mixed-signal functions (e.g. dataconverters and phase locked loops) of a System-on-Chip (SoC) contributes to more than 30% of the total test time, althoughmixed-signal circuits occupy a small fraction of the SoC area that typically does not exceed 5%. Thus, reducing test time forADCs is an area of industry focus and innovation. Pipeline ADCs offer a good compromise between speed, resolution, andpower consumption. They are well-suited for a variety of applications and are typically present in SoCs intended for videoapplications. By virtue of their operation, pipeline ADCs have groups of output codes which have the same width. Thus,instead of considering all the codes in the testing procedure, we can consider measuring only one code out of each group,thus reducing significantly the static test time. In this work, a technique for efficiently applying reduced code testing onpipeline ADCs is proposed. It exploits two main properties of the pipeline ADC architecture and allows obtaining an accurateestimation of the static performances. The technique is validated on an experimental 11-bit, 55nm pipeline ADC fromSTMicroelectronics, resulting in estimated DNL and INL that are practically indistinguishable from DNL and INL that areobtained with the standard histogram technique, while measuring only 6% of the codes.

Ultra low power wireless sensors and sensor systems are of increasing interest in a variety of applications ranging from structural health monitoring to industrial process control. Electrochemical batteries have thus far remained the primary energy sources for such systems despite the finite associated lifetimes imposed due to limitations associated with energy density. However, certain applications (such as implantable biomedical electronic devices and tire pressure sensors) require the operation of sensors and sensor systems over significant periods of time, where battery usage may be impractical and add cost due to the requirement for periodic re-charging and/or replacement. In order to address this challenge and extend the operational lifetime of wireless sensors, there has been an emerging research interest on harvesting ambient vibration energy. Vibration energy harvesting is a technology that generates electrical energy from ambient kinetic energy. Despite numerous research publications in this field over the past decade, low power density and variable ambient conditions remain as the key limitations of vibration energy harvesting. In terms of the piezoelectric transducers, the open-circuit voltage is usually low, which limits its power while extracted by a full-bridge rectifier. In terms of the interface circuits, most reported circuits are limited by the power efficiency, suitability to real-world vibration conditions and system volume due to large off-chip components required. The research reported in this thesis is focused on increasing power output of piezoelectric transducers and power extraction efficiency of interface circuits. There are five main chapters describing two new design topologies of piezoelectric transducers and three novel active interface circuits implemented with CMOS technology. In order to improve the power output of a piezoelectric transducer, a series connection configuration scheme is proposed, which splits the electrode of a harvester into multiple equal regions connected in series to inherently increase the open-circuit voltage generated by the harvester. This topology passively increases the rectified power while using a full-bridge rectifier. While most of piezoelectric transducers are designed with piezoelectric layers fully covered by electrodes, this thesis proposes a new electrode design topology, which maximizes the raw AC output power of a piezoelectric harvester by finding an optimal electrode coverage. In order to extract power from a piezoelectric harvester, three active interface circuits are proposed in this thesis. The first one improves the conventional SSHI (synchronized switch harvesting on inductor) by employing a startup circuitry to enable the system to start operating under much lower vibration excitation levels. The second one dynamically configures the connection of the two regions of a piezoelectric transducer to increase the operational range and output power under a variety of excitation levels. The third one is a novel SSH architecture which employs capacitors instead of inductors to perform synchronous voltage flip. This new architecture is named as SSHC (synchronized switch harvesting on capacitors) to distinguish from SSHI rectifiers and indicate its inductorless architecture.

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.