Evolvable hardware (EHW) uses simulated evolution to generate an electronic circuit with specific characteristics, and is generally implemented on Field Programmable Gate Arrays (FPGAs). EHW has proven to be successful at producing small novel circuits for applications such as robot control and image processing, however, traditional approaches, in which the FPGA configuration is directly encoded on the chromosome, have not scaled well with increases in problem and FPGA architecture complexity. One of the methods proposed to overcome this is the incorporation of a growth process, known as morphogenesis, into the evolutionary process. However, existing approaches have tended to abstract away the underlying architectural details, either to present a simpler virtual FPGA architecture, or a biochemical model that hides the relationship between the cellular state and the underlying hardware. By abstracting away the underlying architectural details, EHW has moved away from one of its key strengths, that being to allow evolution to discover novel solutions free of designer bias. Also, by separating the biological model from the target FPGA architecture, too many assumptions and arbitrary decisions need to be made, which are liable to lead to the growth process failing to produce the desired results. In this thesis a new approach to applying morphogenesis to gate-level FPGA- based EHW is presented, whereby circuit growth is closely tied to the underlying gate-level architecture, with circuit growth being driven largely by the state of gate-level resources of the FPGA. An investigation into the applicability of biological processes, structures and mechanisms to morphogenetic EHW (MGEHW) is conducted, and the resulting design elaborated. The developed MGEHW system is applied to solving a signal routing problem with irregular and severe constraints on routing resources. It is shown that the morphogenetic approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, signal routing problems without any significant increase in the number of generations required to find an optimal solution. With the success of the MGEHW system in solving primarily structural prob- lems, it is then applied to solving a combinatorial function problem, specifically a one-bit full adder, with a more complete set of FPGA resources. The results of these experiments, together with the previous experiments, has provided valuable information that when analysed has enabled the identification of the critical factors that determine the likelihood of an EHW problem being solvable. In particular this has highlighted the importance of effective fitness feedback for guiding evolution towards its desired goal. Results indicate that the gate-level morphogenetic approach is promising. The research presented here is far from complete; many avenues for future research have opened. The MGEHW system that has been developed allows further research in this area to be explored experimentally. Some of the most fruitful directions for future research are described.

Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.

No description available.

No description available.

Master thesis is focused on classification of application protocols based on application data taken from layer L7 of ISO/OSI model. The aim of the thesis is to suggest a classifier for SDM system (Software defined monitoring) so it could be used for links with throughput up to 100 Gb/s. At the same time it should classify with the fewest possible errors.Designed classifier consists of two parts. First part depicts encoders for encoding selected attributes. Second part deals with evaluating circuit which detects series characteristic for particular application protocols on the output from the first part. Considered attributes and series are taken from statistic analyzes of application protocol data.The classifier itself is designed so it can be implemented in FPGA and enables modification set of application protocols who intended for classification. The quality of  designed classifier is tested on real network data. The results of classification are compared with current methods used for classification of application protocols.

Rapid advances in integration technology have tremendously increased the design complexity of very large scale integrated (VLSI) circuits, necessitating robust optimization techniques in many stages of VLSI design. A genetic algorithm (GA) is a stochastic optimization technique that uses principles derived from the evolutionary process in nature. In this work, genetic algorithms are used to alleviate the hardware design process of VLSI application specific integrated circuits (ASICs) and reconfigurable hardware. VLSI ASIC design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. In this work, a multi-objective genetic algorithm based floorplanner has been developed with novel crossover operators to address the multi-objective floorplanning problem for VLSI ASICs. The genetic floorplanner achieves significant wirelength savings (>19% on average) with little or no increase in area ( < 3% penalty) over previous floorplanners that perform simultaneous area and wirelength minimization. Hardware implementation of genetic algorithms is gaining importance because of their proven effectiveness as optimization engines for real-time applications. Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid pre-defined system architecture, and lack of support for multiple fitness functions. A compact IP core that implements a general purpose GA engine has been designed to realize evolvable hardware in field programmable gate array devices. The designed GA core achieved a speedup of around 5.16x over an analogous software implementation. Novel reconfigurable analog architectures have been proposed to realize extreme environment analog electronics. In this work, a digital framework has been developed to realize self reconfigurable analog arrays (SRAA) where genetic algorithms are used to evolve the required analog functionality and compensate performance degradation in extreme environments. The framework supports two methods of compensation, namely, model based lookup and genetic algorithm based compensation and is scalable in terms of the number of fitness evaluation modules. The entire framework has been implemented as a digital ASIC in a leading industrystrength silicon-on-insulator (SOI) technology to obtain high performance and a small form factor.

Orientador: Suely Cunha Amaro Mantovani / Banca: José Raimundo de Oliveira / Banca: Nobuo Oki / Resumo: Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD’s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas). / Abstract: In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices). / Mestre

Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-05-25Bitstream added on 2014-06-13T20:49:18Z : No. of bitstreams: 1 goulartsobrinho_ef_me_ilha.pdf: 944900 bytes, checksum: 47dc5d964428b7cb8bd18e1e00e1d994 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas). / In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-06-01T15:26:09Z No. of bitstreams: 1 franciscoaugustolimamanfrini.pdf: 2355106 bytes, checksum: 0c2126ac87b502d91fbb53cda2fa0b2a (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-06-02T15:56:42Z (GMT) No. of bitstreams: 1 franciscoaugustolimamanfrini.pdf: 2355106 bytes, checksum: 0c2126ac87b502d91fbb53cda2fa0b2a (MD5) / Made available in DSpace on 2017-06-02T15:56:42Z (GMT). No. of bitstreams: 1 franciscoaugustolimamanfrini.pdf: 2355106 bytes, checksum: 0c2126ac87b502d91fbb53cda2fa0b2a (MD5) Previous issue date: 2017-02-23 / A computação evolucionista tem sido aplicada em diversas áreas do conhecimento para a descoberta de projetos inovadores. Quando aplicada na concepção de circuitos digitais o problema da escalabilidade tem limitado a obtenção de circuitos complexos, sendo apontado como o maior problema em hardware evolutivo. O aumento do poder dos métodos evolutivos e da eficiência da busca constitui um importante passo para melhorar as ferramentas de projeto. Este trabalho aborda a computação evolutiva aplicada ao projeto de circuito lógicos combinacionais e cria estratégias para melhorar o desempenho dos algoritmos evolutivos. As três principais contribuições resultam dessa tese são: (i) o desenvolvimento de uma nova metodologia que ajuda a compreensão das causas fundamentais do sucesso/fracasso evolutivo;(ii)a proposta de uma heurística para a semeadura da população inicial; os resultados mostram que existe uma correlação entre a topologia da população inicial e a região do espaço de busca explorada; e (iii) a proposta de um novo operador de mutação denominado Biased SAM; verificou-se que esta mutação pode guiar de maneira efetiva a busca. Nos experimentos realizados o operador proposto é melhor ou equivalente ao operador de mutação tradicional. Os experimentos computacionais que validaram as respectivas contribuições foram feitos utilizando circuitos benchmark da literatura. / Evolutionary computation has been applied in several areas of knowledge for discovering Innovative designs. When applied to a digital circuit design the scalability problem has limited the obtaining of complex circuits, being pointed as the main problem in the evolvable hardware field. Increased power of evolutionary methods and efficiency of the search constitute an important step towards improving the design tool. This work approaches the evolutionary computation applied to the design of combinational logic circuits and createsstrategiestoimprovetheperformanceofevolutionaryalgorithms. The three main contributions result from this thesis are: (i) the developement of a methodology that helps to understand the success/failure of the genetic modifications that occur along the evolution; (ii) a heuristic proposed for seeding the initial population; the results showed there is a correlation between the topology of the initial population and the region of the search space which is explored. (iii) a proposal of a new mutation operator referred to as Biased SAM; it is verified that this operator can guide the search. In the experiments performed the mutation proposed is better than or equivalent to the traditional mutation. The computational experiments that prove the efficiency of the respective contributions were made using benchmark circuits of the literature.

[pt] Esta dissertação propõe uma nova plataforma reconfigurável analógica destinada à síntese de circuitos analógicos utilizando Algoritmos Genéticos. Plataformas Reconfiguráveis pretendem estabelecer uma nova tendência na síntese de circuitos eletrônicos, digitais ou analógicos. Grande interesse é mostrado por parte dos pesquisadores em relação às características de auto-reconfiguração e auto-adaptação presentes nestas plataformas. Estas são características essenciais aos sistemas que precisam funcionar por muito tempo em ambientes hostis, como por exemplo nas missões de exploração espacial. Industrialmente, estas características são desejáveis na produção de equipamentos em chips reconfiguráveis, a fim de diminuir a taxa de equipamentos descartados por estarem fora das especificações, já que neste caso ele seria reconfigurado. Finalmente, de maneira genérica, estas características de auto-reconfiguração e auto-adaptação da plataforma permitem que circuitos sejam sintetizados, otimizados ou reparados através de métodos evolutivos. O desenvolvimento desta dissertação foi realizado em 4 etapas: pesquisa bibliográfica, especificação e implementação da plataforma e estudo de casos. Na primeira etapa buscou-se estudar a área de Eletrônica Evolutiva, verificando suas maiores conquistas e necessidades. Foi dada ênfase à síntese de circuitos analógicos por evolução extrínseca e consequentemente às plataformas reconfiguráveis analógicas desenvolvidas comercialmente e em laboratórios de pesquisa. A especificação e implementação da plataforma por sua vez ocorreu em três fases ou versões, estando envolvidos o projeto conceitual, a implementação e a obtenção e análise dos resultados em cada uma delas. Na primeira versão buscou- se consolidar o projeto inicial, puramente teórico, implementando um protótipo limitado, que pudesse comprovar a capacidade de reconfiguração e evolução e também as desejáveis características de robustez e transparência. Na segunda versão, implementou-se um Circuito Reconfigurável Analógico maior, permitindo que um número maior de blocos construtores fosse conectado à plataforma, consequentemente permitindo que uma variedade maior de circuitos fosse sintetizada. Na terceira versão, com a técnica estudada e devidamente comprovada pelas versões anteriores, buscou-se melhorar o desempenho da plataforma, implementando uma nova interface entre o Circuito Reconfigurável Analógico e o Algoritmo Genético. Realizou- se um estudo de casos em cada uma das versões descritas acima, objetivando comprovar as características e limitações da plataforma proposta. Na primeira versão, diferentes configurações de inversores foram sintetizadas. Na segunda versão sintetizou-se um ou-exclusivo, que serviu como base de comparação de desempenho com a terceira versão. Nesta última versão sintetizou-se um ou-exclusivo, um multiplexador, um amplificador e um amplificador controlado por tensão. Em relação à síntese, os circuitos sintetizados possuem configurações não convencionais, comprovando a capacidade da técnica de explorar características da física do silício. Além disso, os resultados mostram que a plataforma proposta possui as características desejáveis de uma FPAA, tais como robustez, transparência, flexibilidade e a capacidade de auto- reconfiguração. / [en] This dissertation investigates a new analog reconfigurable platform, developed to supply an environment to evolve generic analog circuits based on discrete components, without the need of simulators. Automatic reconfiguration of programmable devices may potentially be driven by Evolutionary Computation techniques such as Genetic Algorithms. Reconfigurable Platforms promise to establish a new trend in electronic design, where a single device now has the flexibility to implement a wide range of electronic circuits, analog or digital. A major interest is shown by researches towards those platforms characteristics of self- adaptation and self- repairing through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Industrially, those features can be applied on analog Evolvable Hardware chip, with the aim to improve the yield rate and produce smaller circuits. This research had four steps: a study of related works, the concept of the platform, it`s implementation and cases studies. In the first step, the focus was to study about Evolvable Hardware, it`s main researches and published work, eferences, and the area actual position. An emphasis has been given to intrinsic evolution, and consequently, to the study of the analog reconfigurable platforms. The concept of the platform and it`s implementation had three steps, and each one of these had its own concept, implementation and experiments steps. The first step aimed at proving the initial concept, totally theoretical. Due to that a limited prototype has been implemented, and the features of self- adaptation through automatic reconfiguration, tranparency and robustness were studied. In the second step, a bigger Reconfigurable Analog Circuit has been developed, allowing the evolution of a wider range of circuits. In the third step, the initial concept of the plataform was already well proved, so the aim was at developing a better interface between the software and the reconfigurable platform to make the evolution faster. In each one of the steps described above a case study has been done. The focus was to study and prove the platform`s characteristics and drawbacks. The experiments taken in the first step were inverter circuit topologies. In the second step an exclusive-or has been synthetized. The evolution time of this experiment was compared to the evolution time of the same experiment evolved in the third step of implementation of the platform. And in this third step, due to the faster interface, other experiments were evolved, such as a multiplexer circuit and an amplifier. The evolved circuits has shown no conventional designs, proving that the evolutionary algorithms can explore some of the regions beyond the scope of conventional me thods, raising the possibility that better designs can be found. The results have also shown that the proposed platform has the desired features of self-adaptation and self-repairing through automatic reconfiguration, transparency, flexibility and robustness. / [es] Esta disertación propone una nueva plataforma analógica reconfigurable destinada a la síntesis de circuitos analógicos utilizando Algoritmos Genéticos. Las Plataformas Reconfigurables pretenden establecer una nueva tendencia en la síntesis de circuitos electrónicos, digitales o analógicos. Existe gran interés por parte de los investigadores en relación a las características de autoreconfiguración y autoadaptación presentes en estas plataformas. Estas características son esenciales en sistemas que necesitan funcionar por mucho tiempo en ambientes hostiles, como por ejemplo en las misiones de exploración espacial. Industrialmente, estas características son deseables en la producción de equipos en chips reconfigurables, A fin de disminuir la tasa de equipos descartados por estar fuera de las especificaciones, ya que en este caso él sería reconfigurado. Finalmente, de manera genérica, estas características de autoreconfiguración y autoadaptación de la plataforma permiten que la sintetización de los circuitos, otimizados o reparados a través de métodos evolutivos. Esta disertación fue realizada en 4 etapas: investigación bibliografía, especificación e implementación de la plataforma y estudio de casos. En la primera etapa se desarrolla un estudio sobre temas de Electrónica Evolutiva, que contempla las mayores conquistas y necesidades de ésta área. Se enfatizó en la síntesis de circuitos analógicos por evolución extrínseca y como consecuencia en las plataformas reconfigurables analógicas desarrolladas comercialmente y en laboratórios de investigación. La especificación e implementación de la plataforma por su vez ocurrió en tres fases o versiones, que involucra el proyecto conceptual, la implementación, obtención y análisis de los resultados en cada una de ellas. En la primera versión se consolida el proyecto inicial, puramente teórico, implementando un prototipo limitado, que pudiese comprobar la capacidad de reconfiguración y evolución y también las características deseables de robustez y transparencia. En la segunda versión, se implementó un Circuito Reconfigurable Analógico mayor, permitiendo conectar un número mayor de bloques constructores, permitiendo así que una variedad mayor de circuitos fuese sintetizada. En la tercera versión, con la técnica estudiada y comprobada por las versiones anteriores, se buscó mejorar el desempeño de la plataforma, implementando uma nueva interfaz entre el Circuito Reconfigurable Analógico y el Algoritmo Genético. Se realizó un estudio de casos en cada una de las versiones descritas acima, con el objetivo de comprobar las características y limitaciones de la plataforma propuesta. En la primera versión, diferentes configuraciones de inversores fueron sintetizadas. En la segunda versión se sintetizó un o-exclusivo, que sirvió como base de comparación del desempeño con la tercera versión. En esta última versión se sintetizó un o-exclusivo, un multiplexador, un amplificador y un amplificador controlado por tensión. En relación a la síntesis, los circuitos sintetizados poseen configuraciones no convencionales, comprobando la capacidad de la técnica de explorar características de la física del silício. Además, los resultados muestran que la plataforma propuesta posee las características deseables de una FPAA, tales como robustez, transparencia, flexibilidad y la capacidad de auto reconfiguración.