Η εργασία αυτή είχε ως σκοπό τη μελέτη της λειτουργίας των κωδικών LDPC, τη χρήση τους σε συστήματα μετάδοσης δεδομένων και την υλοποίησή τους σε κύκλωμα με επεξεργαστές ARM και FPGA. Ο στόχος ήταν να κατασκευαστεί ένα μοντέλο συνεχούς αποστολής και λήψης εικόνων μέσω μη αξιόπιστων μέσων. Αρχικά μελετήσαμε τα θεωρητικά θέματα που αφορούν τους κώδικες LDPC. Μετά ακολούθησε η προσομοίωση των διαδικασιών κωδικοποίησης, αποκωδικοποίησης και η μοντελοποίηση καναλιού. Η εφαρμογή των κωδίκων LDPC βασίστηκε στην προδιαγραφή ETSI EN 302 307. Αυτή η προδιαγραφή αφορά τις δορυφορικές επικοινωνίες και τυποποιεί τις αντίστοιχες εφαρμογές. Το επόμενο βήμα ήταν η υλοποίηση των λειτουργιών του κωδικοποιητή και του αποκωδικοποιητή LDPC. Τέλος, ελέγχθηκε η ορθή λειτουργία των εργασιών κωδικοποίησης και αποκωδικοποίησης και ελήφθησαν οι μετρήσεις σε σχέση με την απόδοση του υλικού. / This thesis was designed to study the function of the LDPC codes, their use in data transmission systems and their implementation in circuit with ARM processors and FPGA. The aim was to construct a model of continuous send and receive pictures via unreliable media (channels introduce errors). Initially we studied the theoretical issues surrounding the LDPC codes. After that we simulated the procedures of coding, decoding and channel modeling. The implementation of LDPC codes was based on the specification ETSI EN 302 307. This specification relates to satellite communications and standardizes the respective applications. The next step was the implementation of the functions of the LDPC encoder and decoder. Finally the proper functioning of coding and decoding operations was checked and measurements relative to the performance of the hardware were taken.

Σκοπός αυτής της διπλωματικής εργασίας είναι η δημιουργία ενός διαδικτυακού σκληρού δίσκου, ο οποίος θα βασίζεται στο ενσωματωμένο επικοινωνιακό σύστήμα Zedboard και το λειτουργικό σύστημα Linux. Χρησιμοποιώντας λοιπόν τον Microsoft iSCSI client θα διαβάζονται και θα γράφονται δεδομένα πάνω στο board, το οποίο θα παίζει ρόλο server. Για την υλοποίηση αυτή θα πρέπει να προγραμματιστεί το board κατάλληλα σύμφωνα με το διαδικτυακό πρωτόκολλο αποθήκευσης iSCSI, έτσι ώστε να μπορεί να ανταλλάσει δεδομένα με τον client. Τελικός στόχος λοιπόν, θα είναι η διαδικτυακή εγγραφή και ανάγνωση δεδομένων από την DRAM του Zedboard, η οποία θα πραγματοποιείται έχοντας σαν βάση το TCP/IP και το διαδικτυακό πρωτόκολλο αποθήκευσης δεδομένων. / --

I dagens samhälle finns inbyggda system i allt från vattenkokare till rymdraketer. För att möta användarnas ständigt ökande krav på prestanda och funktionalitet måste hårdvaran i dessa system utnyttjas optimalt. Detta kan göras genom att konstruera hårdvara specifikt för den aktuella uppgiften eller att använda en mer generell hårdvara, där istället mjukvaran är anpassningsbar. I många fall kan det vara lämpligt, och i vissa fall även nödvändigt, att blanda dessa metoder för att lösa en given uppgift. En kraftfull processor kan exempelvis kompletteras med en accelerator uppbyggd av specifik hårdvara. Delar av lösningen kan genomföras snabbare i dessa acceleratorer vilket leder till ett bättre system. Problemet med denna lösningsmodell är dock att förbindelsen mellan processorn och acceleratorn ofta bildar en flaskhals för data som ska bearbetas. En metod för att minimera denna falskhals är att utveckla både programmerbar logik (FPGA, Field-Programmable Gate Array) och en processor på samma chip. Denna täta integration gör det möjligt att både förenkla och snabba upp kommunikationen mellan FPGA och processor. Xilinx har utvecklat ett sådant system, Zynq-7000, uppbyggd av en dubbelkärning ARM-processor och en kraftfull FPGA. Denna rapport beskriver det arbete som har utförts under detta examensarbete. Syftet med examensarbetet var att undersöka hur en specifik produktprototyp kan implementeras i Zynq-7000. Fokus för arbetet var att undersöka hur den interna kommunikationen bör genomföras och därigenom även hur lösningen bör partitioneras mellan mjukvara och hårdvara. Den tänkta produkten var ett system för bildigenkänning av frukter eller grönsaker för användning i en livsmedelsbutik. Under arbetet har utvecklingskortet ZedBoard, baserat på Zynq-7000, använts som målplattform. / In today's society there are embedded systems in almost everything from toasters to space rockets. In order to meet users’ ever-increasing demands for performance and functionality, the hardware of these systems must be utilized optimally. This can be done by designing hardware specifically for the task, or to use a more general hardware running customizable software. In many cases it may be suitable, and in some cases even necessary, to mix these methods to solve a given task. For example, a powerful processor could be complemented with special designed hardware, called an accelerator, to solve parts of the problem faster. The overall system performance can thus be increased by the use of the accelerators. One problem with this solution is that the connection between the processor and the accelerator may form a bottleneck. One way to reduce the effects of this bottleneck is to tightly integrate programmable logic (FPGA, Field Programmable Gate Array) and a processor on the same chip. This tight integration makes it possible to simplify and speed up the communication between the two units. For example, image processing could be accelerated in the FPGA and the result could then be used in some software application in the processor. This report describes how the work was carried out during this thesis. The main goal of the thesis was to study how a specific product prototype could be implemented using a Zynq-7000 based development board. The focus of this work was to study how the internal communication should be implemented, and there by how the solution should be partitioned between the software and hardware in Zynq-7000. The intended product was a system for image recognition of fruits or vegetables for use in a grocery store. During the work we used a Zynq-7000 based development board called ZedBoard to try our implementations.

Ces dernières années, les systèmes informatiques (Cloud Computing, systèmes embarqués, etc.) sont devenus omniprésents. La plupart de ces systèmes utilisent des espaces de stockage (flash,RAM, etc.) non fiables ou non dignes de confiance pour stocker du code ou des données. La confidentialité et l’intégrité de ces données peuvent être menacées par des attaques matérielles (espionnage de bus de communication entre le composant de calcul et le composant de stockage) ou logicielles. Ces attaques peuvent ainsi révéler des informations sensibles à l’adversaire ou perturber le bon fonctionnement du système. Dans cette thèse, nous nous sommes focalisés, dans le contexte des systèmes embarqués, sur les attaques menaçant la confidentialité et l’intégrité des données qui transitent sur le bus de communication avec la mémoire ou qui sont stockées dans celle-ci.Plusieurs primitives de protection de confidentialité et d’intégrité ont déjà été proposées dans la littérature, et notamment les arbres de Merkle, une structure de données protégeant efficacement l’intégrité des données notamment contre les attaques par rejeu. Malheureusement,ces arbres ont un impact important sur les performances et sur l’empreinte mémoire du système.Dans cette thèse, nous proposons une solution basée sur des variantes d’arbres de Merkle (arbres creux) et un mécanisme de gestion adapté du cache afin de réduire grandement l’impact de la vérification d’intégrité d’un espace de stockage non fiable. Les performances de cette solution ont été évaluées théoriquement et à l’aide de simulations. De plus, une preuve est donnée de l’équivalence, du point de vue de la sécurité, avec les arbres de Merkle classiques.Enfin, cette solution a été implémentée dans le projet SecBus, une architecture matérielle et logicielle ayant pour objectif de garantir la confidentialité et l’intégrité du contenu des mémoires externes d’un système à base de microprocesseurs. Un prototype de cette architecture a été réalisé et les résultats de l’évaluation de ce dernier sont donnés. / During the past few years, computer systems (Cloud Computing, embedded systems...) have become ubiquitous. Most of these systems use unreliable or untrusted storage (flash, RAM...)to store code or data. The confidentiality and integrity of these data can be threaten by hardware (spying on the communication bus between the processing component and the storage component) or software attacks. These attacks can disclose sensitive information to the adversary or disturb the behavior of the system. In this thesis, in the context of embedded systems, we focused on the attacks that threaten the confidentiality and integrity of data that are transmittedover the memory bus or that are stored inside the memory. Several primitives used to protect the confidentiality and integrity of data have been proposed in the literature, including Merkle trees, a data structure that can protect the integrity of data including against replay attacks. However, these trees have a large impact on the performances and the memory footprint of the system. In this thesis, we propose a solution based on variants of Merkle trees (hollow trees) and a modified cache management mechanism to greatly reduce the impact of the verification of the integrity. The performances of this solution have been evaluated both theoretically and in practice using simulations. In addition, a proof a security equivalence with regular Merkle treesis given. Finally, this solution has been implemented in the SecBus architecture which aims at protecting the integrity and confidentiality of the content of external memories in an embedded system. A prototype of this architecture has been developed and the results of its evaluation are given.

New methods for monitoring the condition of roller element bearings in rotating machinery offer possibilities to reduce repair- and maintenance costs, and reduced use of environmentally harmful lubricants. One such method is sparse representation of vibration signals using matching pursuit with dictionary learning, which so far has been tested on PCs with data from controlled tests. Further testing requires a platform capable of signal processing and control in more realistic experiments. This thesis focuses on the integration of a hybrid CPU-FPGA hardware system with a 16-bit analog-to-digital converter and an oil pump, granting the possibility of collecting real-time data, executing the algorithm in closed loop and supplying lubrication to the machine under test, if need be. The aforementioned algorithm is implemented in a Zynq-7000 System-on-Chip and the analog-to-digital converter as well as the pump motor controller are integrated. This platform enables portable operation of the matching pursuit with dictionary learning in the field under a larger variety of environmental and operational conditions, conditions which might prove difficult to reproduce in a laboratory setup. The platform developed throughout this project can collect data using the analog-to-digital converter and operations can be performed on that data in both the CPU and the FPGA. A test of the system function at a sampling rate of 5 kHz is presented and the input and output are verified to function correctly.

This thesis contains introduction to PMS motor control using development board ZedBoard with Xilinx Zynq-7000 SoC. After that, there is a description of development environment Vivado and other modules. Finally, it contains description or created modules in Vivado environment which were combined together with peripheral drivers to demonstrate field oriented motor control algorithm of small PMS motor.

Indiana University-Purdue University Indianapolis (IUPUI) / In recent years, Convolutional Neural Networks (CNNs) have become the state-of- the-art method for object detection and classi cation in the eld of machine learning and arti cial intelligence. In contrast to a fully connected network, each neuron of a convolutional layer of a CNN is connected to fewer selected neurons from the previous layers and kernels of a CNN share same weights and biases across the same input layer dimension. These features allow CNN architectures to have fewer parameters which in turn reduces calculation complexity and allows the network to be implemented in low power hardware. The accuracy of a CNN depends mostly on the number of images used to train the network, which requires a hundred thousand to a million images. Therefore, a reduced training alternative called transfer learning is used, which takes advantage of features from a pre-trained network and applies these features to the new problem of interest. This research has successfully developed a new CNN based on the pre-trained CIFAR-10 network and has used transfer learning on a new problem to classify road edges. Two network sizes were tested: 32 and 16 Neuron inputs with 239 labeled Google street view images on a single CPU. The result of the training gives 52.8% and 35.2% accuracy respectively for 250 test images. In the second part of the research, High Level Synthesis (HLS) hardware model of the network with 16 Neuron inputs is created for the Zynq 7000 FPGA. The resulting circuit has 34% average FPGA utilization and 2.47 Watt power consumption. Recommendations to improve the classi cation accuracy with deeper network and ways to t the improved network on the FPGA are also mentioned at the end of the work.

This thesis deals with the modifications of the hardware design and operating systems of the ZedBoard multi-core platform so that both ARM Cortex A9 processor cores included in SoC Zynq7000 can be used. It analyses the general issue of the multi-core environment and the core functions of the kernel and the operating system. It describes selected means of implementation ZedBoard and FreeRTOS. In the implementation section, specific steps are demonstrated to convert a single-core operating system to a multi-core system but also steps required to run two different operating systems on two processor cores. In the last section all achieved results are summarized.

This thesis discuss necessary changes needed in order to run MicroC/OS-II on multicore processor, mainly Zynq 7000 All Programmable SoC which uses two ARM Cortex-A9 cores. Problems that arise during this transition are also discussed.