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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator

Åkerman, Markus January 2005 (has links)
<p>In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. The schematics are important to get a better overview, to test parts properly, and enable Layout versus Schematics (LVS) checks.</p><p>The main focus of this thesis work is to implement and evaluate a new SRAM cell, called Zero Aware Asymmetric SRAM cell. This cell saves major power when zeros are stored. Furthermore the pull-up circuit is modified to be less power consuming. Other parts are also modified to fit the new memory cell.</p><p>Several minor flaws are corrected in the layout generator. It does still not produce a complete memory without manual interventions, but it does at least create all parts with one command. Several tests, including Design Rule Checks (DRC) and LVS checks, are carried out both on minor and larger parts. Development of documentation that makes it easier for users and developers to use and understand the tool is initiated.</p>
2

Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator

Åkerman, Markus January 2005 (has links)
In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. The schematics are important to get a better overview, to test parts properly, and enable Layout versus Schematics (LVS) checks. The main focus of this thesis work is to implement and evaluate a new SRAM cell, called Zero Aware Asymmetric SRAM cell. This cell saves major power when zeros are stored. Furthermore the pull-up circuit is modified to be less power consuming. Other parts are also modified to fit the new memory cell. Several minor flaws are corrected in the layout generator. It does still not produce a complete memory without manual interventions, but it does at least create all parts with one command. Several tests, including Design Rule Checks (DRC) and LVS checks, are carried out both on minor and larger parts. Development of documentation that makes it easier for users and developers to use and understand the tool is initiated.

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