The CubeSat standard sprang from the desire to create a satellite standard that would open the doors for universities and other lower budget research institutions by making it more feasible to get their work into space. Since then, many other institutions and industries have been adopting variations on the standard for their own use. As more people are seeking out to use the CubeSat standard as their main bus, the standards and practices of the community have grown and expanded and with this growth, new challenges have been created. One such challenge is the bandwidth limitation in the RF-downlink. When carrying payloads requiring what might seem to be a relatively small (science data) bandwidth requirement (on the order of thousands of bps), the RF-link to ground is overloaded. Many approaches in the past have been put forth to help alleviate this issue, unfortunately, none have been fully adopted. This paper presents a solution that takes advantage of new technology yet to be fully exploited in space applications. The key to the solution lies in removing the bandwidth requirements by enabling onboard post-data processing and compression. In order to achieve the high computational needs, while minimizing power consumption, a Xilinx Zynq-7000 SoC is used, creating a highly-programmable, open integration device. This report outlines the design, fabrication and testing of this solution. The completion of the Zynq Processing System CubeSat Science Instrument Interface Electronics Board (or ZPS-Board), ultimately demonstrates the feasibility of this solution. Additionally, this research is funded by NASA’s JPL, with secondary motives for the creating of a space application Zynq-7000 SoC based product. Upon successful completion of the ZPS-Board, the product creates a platform for JPL to perform environmental testing in order to study the effects and performance characteristics of the Zynq in space applications.

Indiana University-Purdue University Indianapolis (IUPUI) / In autonomous driving, medical diagnosis, unmanned vehicles and many other new technologies, the neural network and computer vision has become extremely popular and influential. In particular, for classifying objects, convolutional neural networks (CNN) is very efficient and accurate. One version is the Region-based CNN (RCNN). This is our selected network design for a new implementation in an FPGA. This network identifies stop signs in an image. We successfully designed and trained an RCNN network in MATLAB and implemented it in the hardware to use in an embedded real-world application. The hardware implementation has been achieved with maximum FPGA utilization of 220 18k BRAMS, 92 DSP48Es, 8156 FFS, 11010 LUTs with an on-chip power consumption of 2.235 Watts. The execution speed in FPGA is 0.31 ms vs. the MATLAB execution of 153 ms (on the computer) and 46 ms (on GPU).

Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. The TDC is used to measure the time between received data in a QKD application. If the measuredtime does not exceed a certain value then data had been sent without any interception. It is alsopossible to use TDCs in other fields such as laser-ranging and time-of-flight applications. The TDC consists of two carry chains, an encoder, a FIFO and a counter for each channel, anAXI-module and a control unit to generate command signals to all channels that are implemented.The time is measured by sampling the signal that has propagated through the carry chain and from thissample encode the propagation length. In this thesis a TDC is implemented that has a 10 ns dead time and a resolution below 28 psin a four channel mode. The propagation variation is approximately two percent of the total valueduring testing. For the implementation an FPGA-board with a Zynq XC7Z020 SoC is used withSystemVerilog that is a hardware describing language (HDL).

This work investigates the interface and properties of an ionization radiation detector with the PhPix chip, which is the basis of a future large-scale detector for use in nuclear medicine. In the next stage, an IP core for communication between the processor system and the PhPix chips on the Zynq platform is designed. Furthermore, software for video transmission over Ethernet interface is developed.

The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software defined radio applications. The addition of FPGAs to these flexible systems has resulted in platforms that can address a multitude of applications with performance levels that were once only known to ASICs. This work presents an embedded heterogeneous scalable cluster platform with software defined radio applications. The Xilinx Zynq chip provides a hybrid platform consisting of an embedded ARM general-purpose processing core and a low-power FPGA. The ARM core provides all of the benefits and ease of use common to modern high-level software languages while the FPGA segment offers high performance for computationally intensive components of the application. Four of these chips were combined in a scalable cluster and a task assigner was written to automatically place data flows across the FPGAs and ARM cores. The rapid reconfiguration software tFlow was used to dynamically build arbitrary FPGA images out of a library of pre-built modules. / Master of Science

Submitted by Alison França Queiroz da Costa (alisonfqc@gmail.com) on 2019-01-23T16:24:02Z No. of bitstreams: 1 dissertacao_Alison_Franca.pdf: 3877983 bytes, checksum: 3ca6152176a6c8ec61d124d98c1623ee (MD5) / Approved for entry into archive by Cristina Alexandra de Godoy null (cristina@adm.feis.unesp.br) on 2019-01-28T12:25:06Z (GMT) No. of bitstreams: 1 costa_afq_me_ilha.pdf: 4321708 bytes, checksum: 13ff971f8fa75010bf9d693777aac778 (MD5) / Made available in DSpace on 2019-01-28T12:25:06Z (GMT). No. of bitstreams: 1 costa_afq_me_ilha.pdf: 4321708 bytes, checksum: 13ff971f8fa75010bf9d693777aac778 (MD5) Previous issue date: 2018-12-21 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Este trabalho desenvolveu um protótipo de um correlacionador de sinais aplicados a vazamento em tubulações de água aterrada. Para tal foi analisado o SoC Zynq, utilizando a placa Minized juntamente com um conversor analógico-digital, Pmod AD1, um módulo GPS, Pmod GPS, um clock em tempo real, Pmod RTCC e um modulo acelerômetro Pmod NAV. Nesta análise foram utilizados modelos criados no software Xilinx Vivado, baseados em Intellectual Property blocks, e o software Xilinx SDK. A partir dos modelos desenvolvidos foram realizados testes com o propósito de validar o sincronismo entre as placas. Inicialmente testou-se um modelo simples apenas utilizando a placa e o módulo Pmod AD1, sendo o teste realizado para verificar a resolução do relógio da placa Minized. Em seguida foi feito o experimento com a placa Minized e o Pmod RTCC visando o sincronismo entre as placas. Os testes de sincronismo foram finalizados utilizando-se o conjunto Minized, Pmod RTCC e Pmod GPS, que obteve bons resultados. Para a finalização da análise da correlação de sinais verificou-se a utilização do Pmod NAV para a aquisição de dados com testes em bancada, apresentando resultados experimentais satisfatórios. / This work developed a prototype of a signal correlator applied to leakage in buried water pipes. The Zynq SoC was analyzed using the Minized board together with an analog-to-digital converter, Pmod AD1, a module GPS, Pmod GPS, a real-time clock, Pmod RTCC and a Pmod NAV accelerometer module. For this analysis we used models created in the Xilinx Vivado software, based on Intellectual Property blocks, and the Xilinx SDK software. From the developed models tests were carried out in order to validate the synchronism between the boards. Initially, a simple model was tested using only the board and the module Pmod AD1, and the test was performed to verify the resolution of the Minized board's clock. Then the experiment was performed using the Minized board and the Pmod RTCC aiming the synchronism between the boards. In order to finalize the synchronization tests, we used the Minized set, Pmod RTCC and Pmod GPS, which presented good results. For the conclusion of the analysis of the correlation of signals, the use of the Pmod NAV for the data acquisition was verified and then benchmarked, presenting satisfactory experimental results. / FAPESP: 2016/24974-2 / CAPES: Código de Financiamento 001

Orientador: Ailton Akira Shinoda / Resumo: Este trabalho desenvolveu um protótipo de um correlacionador de sinais aplicados a vazamento em tubulações de água aterrada. Para tal foi analisado o SoC Zynq, utilizando a placa Minized juntamente com um conversor analógico-digital, Pmod AD1, um módulo GPS, Pmod GPS, um clock em tempo real, Pmod RTCC e um modulo acelerômetro Pmod NAV. Nesta análise foram utilizados modelos criados no software Xilinx Vivado, baseados em Intellectual Property blocks, e o software Xilinx SDK. A partir dos modelos desenvolvidos foram realizados testes com o propósito de validar o sincronismo entre as placas. Inicialmente testou-se um modelo simples apenas utilizando a placa e o módulo Pmod AD1, sendo o teste realizado para verificar a resolução do relógio da placa Minized. Em seguida foi feito o experimento com a placa Minized e o Pmod RTCC visando o sincronismo entre as placas. Os testes de sincronismo foram finalizados utilizando-se o conjunto Minized, Pmod RTCC e Pmod GPS, que obteve bons resultados. Para a finalização da análise da correlação de sinais verificou-se a utilização do Pmod NAV para a aquisição de dados com testes em bancada, apresentando resultados experimentais satisfatórios. / Abstract: This work developed a prototype of a signal correlator applied to leakage in buried water pipes. The Zynq SoC was analyzed using the Minized board together with an analog-to-digital converter, Pmod AD1, a module GPS, Pmod GPS, a real-time clock, Pmod RTCC and a Pmod NAV accelerometer module. For this analysis we used models created in the Xilinx Vivado software, based on Intellectual Property blocks, and the Xilinx SDK software. From the developed models tests were carried out in order to validate the synchronism between the boards. Initially, a simple model was tested using only the board and the module Pmod AD1, and the test was performed to verify the resolution of the Minized board's clock. Then the experiment was performed using the Minized board and the Pmod RTCC aiming the synchronism between the boards. In order to finalize the synchronization tests, we used the Minized set, Pmod RTCC and Pmod GPS, which presented good results. For the conclusion of the analysis of the correlation of signals, the use of the Pmod NAV for the data acquisition was verified and then benchmarked, presenting satisfactory experimental results. / Mestre

No description available.

This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.

The goal of this thesis is how to implement the two different types of the electric alternate motors in ZYNQ-7000 device for MIL real-time simulation purposes. The chosen types of motors are BLDC motor and AC induction motor. Mathematics models of these motor, the necessary changes for implementation purposes and the way how the models were implemented in ZYNQ-7000 device are described in this work. Three different experimental MIL simulation, using these motors ae described at the end of this thesis.