In this thesis, we will investigate the degradation of the low temperature polycrystalline silicon TFTs (LTPS TFTS) under the electrical stress. The electrical stress is divided into two parts of ac stress and dc stress. We used ac stress and dc stress conditions to stress different TFTs respectively and investigate the influence of grain boundary in n-type TFT and p-type TFT by use of electrical analysis. On the other hand, degradation mechanism was confirmed by measured capacitance. In n-type TFT, the SLS poly-Si TFT which contains GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ISE_TCAD). In p-type TFT, the enhancement phenomenon is always observed after dc or ac stress. There are both existed a power-law between the variation of the drain current with stress time. The slope of power-law is related to the shortening speed of effective channel length. In either dc stress or ac stress, there are two effective factors. The one factors of them is the degradation of poly-Si film, and another one is the effective channel length shortening. In the competition of these two effective factors, the GB-TFT has more obvious enhancement than GB-TFT during dc stress. Nevertheless, during the ac stress the GB-TFT is without larger enhancement than NGB-TFT because of serious poly-Si film damage.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

In this research, the degradation effect of the low temperature polycrystalline silicon TFTs (LTPS TFTs) under dynamic stress was investigated. The experiment results revealed that the degenerate behaviors of n- and p-type poly-Si were different. In p-channel TFT, it was observed that the degradation of threshold-voltage (Vth) was closely associated with the stress frequency of ac stress. The degradation was more serious at low-frequency stress than that at high-frequency stress. The degradation of electrical characteristics of device is mainly dominated by the self-heating enhanced negative bias temperature instability effect. Moreover, the increased temperature around the environment could make the degradation of characteristics more serious, such as Vth shift (fixed charge), degraded S.S (dangling bonds). We suggest that the generation of deep states originated from bond broken at both of grain-boundary and interface state was explained the degradation mechanism of threshold-voltage. In n-channel TFT, the degradation characteristics may be attributed to both of the temperature effect and the hot carrier effect under the different stress frequency. At low-frequency stress, Vth shift (positively) and mobility are increased after 100 seconds stress because of the temperature effect. However, Vth shift (negatively) and mobility are decreased after 500 seconds stress because of the effect of the state creation near the drain regime. At high-frequency stress, the times of the switch is numerous, and result in the on-state current decreased because of the trap state generated.

Since the traditional CRT(Cathode Ray Tube) replaced by FPD(Flat Panel Display), e.g. LCD¡BOLED¡BPDP, FPD industry is regarded as the important one of global industry following Semi-conductor industry. The main stream of Large-Area Displays is TFT-LCD(Thin Film Transistor-Liquid Crystal Display) and it¡¦s applied a-Si:H TFT (the hydrogenated Amorphous Silicon Thin Film Transistor) as pixel-switch device on LCD. In a-Si:H TFT Cell process, the active region material(a-Si:H) with higher Photoconductivity results into higher off-state current under light illumination and that causes color performance discrepancy as incomplete On/Off operation of pixel-switch devices. As long as the introduction of F into a-Si:H modify the density of states in the gap of a-Si:H(:F), that may result the shift of the Fermi level toward the valence band edge and The density-of-states increasing. It¡¦s effective to decrease the photo leakage current. Due to electro-optical properties of liquid crystal(LC), to drive Pixel-switch device in TFT-LCD shall force On/Off voltage to change Twist Angle of LC is corresponding to have Stress on TFT device. According to DC Stress experiment results, it¡¦s found TFT device with SiF4 dopant can reach better reliability. This issue is aimed to research the photo leakage current variation of a-Si:H TFT at low temperature and ON/Off state effect by stress on TFT device.

Dans le but de développer un modèle compact spécifique aux transistors en couches minces (TFT) à base de silicium amorphe ou microcristallin, nous présentons dans ce manuscrit nos études sur l'optimisation des modèles compacts et des méthodes d'extraction des paramètres et, surtout, différents phénomènes présents dans la physique de ces TFTs. Nous proposons une méthode plus robuste d'extraction des paramètres, qui, différemment des méthodes conventionnelles, ne néglige pas la résistance d'accès, diminuant ainsi la subjectivité du procédé de l'extraction. La résistance d'accès dans les différentes structures a été analysée. Pour la structure top-gate coplanar, nous nous sommes focalisés sur des raisons géométriques pour montrer la dépendance de la résistance d'accès en tension de grille. Pour la structure bottom-gate staggered, nous avons introduit l'approche de transport-diffusion au modèle de current crowding, en prouvant la dépendance en tension de grille et en courant en raison de la diffusion des électrons. Le comportement dynamique a été étudié en couplant mesures expérimentales et simulations par éléments finis, en associant les capacités intrinsèques des TFTs avec le temps de retard d'allumage. Nous avons observé l'évolution temporelle du canal lors de sa création ou de sa disparition et nous avons ainsi proposé un modèle qui décrit sa propagation dans un TFT. Nous avons enfin étudié le phénomène de vieillissement des TFTs et nous avons mis en évidence la localisation de la dégradation et de la relaxation dans un TFT sous un stress électrique avec la tension de drain non-nulle.