To make energy production sustainable and reduce carbon dioxide emissions it is necessary to stop using fossil fuels as our primary energy source. The Accelerator Driven Subcritical Reactor (ADSR) could provide safe nuclear power. It uses thorium as fuel, which is more abundant than uranium, and produces less long lived waste. An ADSR uses neutron spallation, caused by a high power proton beam impacting a metal target, to drive and control the reaction. The beam needs to have an energy of around 1 Ge V and a current of 10 mA with a very high reliability, the combination of which is beyond the capabilities of existing particle accelerators. Cyclotrons and synchrotrons both have trouble producing such a beam, while a suitable linac would be several hundred metres long, and expensive. A more compact accelerator design would allow multiple accelerators to be combined to improve reliability. This thesis examines the use of a Fixed-Field Alternating-Gradient (FFAG) accelerator as the proton driver. FFAGs are compact, and can simultaneously achieve higher energies than a cyclotron at higher repetition rates than a synchrotron. However, it is still a challenge to reach the high currents required. A 35 to 400 MeV non-scaling FFAG was designed to demonstrate issues encountered at high currents. Two methods were investigated in order to increase the number of particle bunches that could be simultaneously accelerated. One uses multiple solutions to the harmonic conditions for acceleration, and the second injects bunches after the acceleration has started. Neither was found to give significant practical improvement in current. Space charge is a destructive force at high currents. Software was developed to simulate the effect of space charge in an FFAG using several models. Space charge tune shifts were measured for a range of energies and currents, and peak currents of above 1 A were found to be unstable. In order to provide 10 mA of average current, acceleration would need to occur in around 100 turns, which will require a very rapid RF sweep.

Cette thèse présente le développement d'un système de contrôle en temps réel basé sur un détecteur en diamant pour la nouvelle source de rayons gamma en cours de construction à Magurele, en Roumanie, pour le projet Extreme Light Infrastructure (ELI). La machine comprend un accélérateur linéaire d'électrons qui se sépare en deux lignes, une à basse énergie entre 80 et 320 MeV et l'autre à plus haute énergie pouvant atteindre 720 MeV. Sur les deux lignes, un recirculateur optique guide un laser haute puissance pour entrer en collision avec 32 paquets d'électrons afin de produire des rayons gamma par interaction Compton inverse. Cette machine est construite par le consortium européen EuroGammaS, dont le Laboratoire de l'Accélérateur Linéaire fait partie et qui a pour mission de développer la plupart des composants optiques. C'est aussi là où j'ai préparé le travail présenté dans ce manuscrit. Les paquets d'électrons séparés de 16 ns collisionneront avec une impulsion laser à une fréquence de 100 Hz. Pour s'assurer de la qualité et de la stabilité de ces interactions, le système du détecteur diamant a été mis en place. Cela a impliqué du travail de simulation sous GEANT4 ainsi que des expériences pour tester l'équipement à HiGS aux Etats-Unis et à newSubaru au Japon, deux établissements scientifiques qui proposent aussi des sources de rayons gamma produits par interaction Compton inverse. Les résultats obtenus démontrent l'efficacité de ce système en analysant l'efficacité de détection, la charge collectée ou encore la forme de faisceau. Ceci est encourageant en vue de l'installation et du commissioning qui sont attendus pour 2019. / This thesis discusses the development of a real-time monitoring system based on a diamond detector for the new gamma source being built in Magurele, Romania as part of the Extreme Light Infrastructure (ELI) project. The machine consists of an electron linear accelerator that branches into two lines, one at low energy between 80 and 320 MeV and one at higher energy going up to 720 MeV. On both lines, an optical recirculator leads a high power laser to collide with 32 electrons bunches to produce gamma rays by inverse Compton interaction. This machine is built by a European consortium named EuroGammaS, of which the "Laboratoire de l'Accélérateur Linéaire" is a member and tasked with developing most of the optical components. This is where I prepared the work presented in this manuscript. The electron bunches separated by 16 ns will collide with a circulating laser pulse at a rate of 100 Hz. To monitor the quality and stability of these interactions, the diamond detector system has been set-up. This involved simulation work on GEANT4 as well as two experiments to test the equipment at HiGS in the USA and newSubaru in Japan, two facilities that also offer gamma ray beams produced by inverse Compton scattering. The results obtained demonstrate the effectiveness of the system by analysing detection efficiency, charge collected or beam shape. This is promising in anticipation of the installation and commissioning expected for 2019.

abstract: In the era of artificial intelligent (AI), deep neural networks (DNN) have achieved accuracy on par with humans on a variety of recognition tasks. However, the high computation and storage requirement of DNN training and inference have posed challenges to deploying or locally training the DNNs on mobile and wearable devices. Energy-efficient hardware innovation from circuit to architecture level is required.In this dissertation, a smart electrocardiogram (ECG) processor is first presented for ECG-based authentication as well as cardiac monitoring. The 65nm testchip consumes 1.06 μW at 0.55 V for real-time ECG authentication achieving equal error rate of 1.7% for authentication on an in-house 645-subject database. Next, a couple of SRAM-based in-memory computing (IMC) accelerators for deep learning algorithms are presented. Two single-array macros titled XNOR-SRAM and C3SRAM are based on resistive and capacitive networks for XNOR-ACcumulation (XAC) operations, respectively. XNOR-SRAM and C3SRAM macros in 65nm CMOS achieve energy efficiency of 403 TOPS/W and 672 TOPS/W, respectively. Built on top of these two single-array macro designs, two multi-array architectures are presented. The XNOR-SRAM based architecture titled “Vesti” is designed to support configurable multibit activations and large-scale DNNs seamlessly. Vesti employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the write latency of IMC SRAMs. The Vesti accelerator in 65nm CMOS achieves energy consumption of <20 nJ for MNIST classification and <40μJ for CIFAR-10 classification at 1.0 V supply. More recently, a programmable IMC accelerator (PIMCA) integrating 108 C3SRAM macros of a total size of 3.4 Mb is proposed. The28nm prototype chip achieves system-level energy efficiency of 437/62 TOPS/W at 40 MHz, 1 V supply for DNNs with 1b/2b precision. In addition to the IMC works, this dissertation also presents a convolutional neural network (CNN) learning processor, which accelerates the stochastic gradient descent (SGD) with momentum based training algorithm in 16-bit fixed-point precision. The65nm CNN learning processor achieves peak energy efficiency of 2.6 TOPS/W for16-bit fixed-point operations, consuming 10.45 mW at 0.55 V. In summary, in this dissertation, several hardware innovations from circuit to architecture level are presented, exploiting the reduced algorithm complexity with pruning and low-precision quantization techniques. In particular, macro-level and system-level SRAM based IMC works presented in this dissertation show that SRAM based IMC is one of the promising solutions for energy-efficient intelligent systems. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

abstract: QR decomposition (QRD) of a matrix is one of the most common linear algebra operationsused for the decomposition of a square/non-square matrix. It has a wide range of applications especially in Multiple Input-Multiple Output (MIMO) communication systems. Unfortunately it has high computation complexity { for matrix size of nxn, QRD has O(n3) complexity and back substitution, which is used to solve a system of linear equations, has O(n2) complexity. Thus, as the matrix size increases, the hardware resource requirement for QRD and back substitution increases signicantly. This thesis presents the design and implementation of a exible QRD and back substitution accelerator using a folded architecture. It can support matrix sizes of 4x4, 8x8, 12x12, 16x16, and 20x20 with low hardware resource requirement. The proposed architecture is based on the systolic array implementation of the Givens algorithm for QRD. It is built with three dierent types of computation blocks which are connected in a 2-D array structure. These blocks are controlled by a scheduler which facilitates reusability of the blocks to perform computation for any input matrix size which is a multiple of 4. These blocks are designed using two basic programming elements which support both the forward and backward paths to compute matrix R in QRD and column-matrix X in back substitution computation. The proposed architecture has been mapped to Xilinx Zynq Ultrascale+ FPGA (Field Programmable Gate Array), ZCU102. All inputs are complex with precision of 40 bits (38 fractional bits and 1 signed bit). The architecture can be clocked at 50 MHz. The synthesis results of the folded architecture for dierent matrix sizes are presented. The results show that the folded architecture can support QRD and back substitution for inputs of large sizes which otherwise cannot t on an FPGA when implemented using a at architecture. The memory sizes required for dierent matrix sizes are also presented. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2020

abstract: X-ray free electron lasers (XFELs) provide several orders of magnitude brighter x-rays than 3rd generation sources. However, the electron beamlines and undulator magnets required are on the scale of kilometers, costing billions of dollars with only a half dozen or so currently operating worldwide. One way to overcome these limitations is to prebunch the electron beam on the scale of the x-ray wavelength. In this paper one such scheme is discussed, which uses a nanopatterned grating called a dynamical beam stop. This uses diffraction from crystal planes of the etched portion of a grating to impart a transverse modulation which becomes a temporal modulation via an emittance exchange (EEX). To expand upon this topic, dynamical electron diffraction intensities for a 200 nm thick Si(001) unpatterned membrane are simulated via the multislice method and compared to experiment for various crystallographic orientations at MeV energies. From this as well as an analysis of the experimental inelastic plasmon diffuse scattering, it is determined that the optimal transverse modulation would be formed from a bright field image of the beam stop, with the nanopattern being etched all the way through the membrane. A model quantifying the quality of the modulation - the bunching factor - as a function of contrast and duty factor is formulated and the optimal modulation is determined analytically. A prototype beam stop is then imaged in a transmission electron microscope (TEM) at 200 KeV, with the measured bunching factor of 0.5 agreeing with the model and approaching a saturated XFEL. Using the angular spectrum method, it is determined that the spatial coherence of the MeV energy electron beam is insufficient for significant self-imaging to occur for gratings with pitches of hundreds of nanometers. Finally, the first-order EEX input requirements for the electron beam are examined in the transverse dimension as are newly proposed longitudinal requirements to compensate for lingering correlations between the initial and final longitudinal phase spaces. / Dissertation/Thesis / Doctoral Dissertation Physics 2020

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(情報学) / 甲第23325号 / 情博第761号 / 新制||情||130(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 大木 英司, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Deep Neural Networks are state-of the art algorithms for various image and natural language processing tasks. These networks are composed of billions of operations working on an input to produce the desired result. Along with this computational complexity, these workloads are also massively parallel in nature. These inherent properties make deep neural networks an excellent target for custom acceleration. The main challenge faced by such accelerators is achieving a compromise between power consumption, software programmability, and resource utilization for the varied compute and data access patterns presented by DNN workloads. In this work, I present Inference Engine, a scalable and efficient DNN accelerator designed to be agnostic to the type of DNN workload. Inference Engine was designed to provide near peak hardware resource utilization, minimize data transfer, and offer a programmer friendly instruction set. Inference engine scales at the level of individually programmable clusters, each of which contains several hundred compute resources. It provides an instruction set designed to exploit parallelism within the workload while also allowing freedom for compiler based exploration of data access patterns.

The aim of this diploma thesis is the design of linear accelerator for oncology treatment. The design focuses on the improvement of the aesthethical side of the accelator, but also comes up with inventional solutions how to improve the radiation treatment of oncology patients to higher the chances of successful treatment of cancer.

This report explains how an SMES is operated and how SMES systems could be used to increase the efficiency of the CERN Large Hadron Collider (LHC) and the Future Circular Collider (FCC) as well as to reduce the very high power needs of a future Muon Collider (MC). The performance of SMES for other applications and late developments of the technique will also be described.

Convolutional neural networks (CNNs) have been extensively used in many aspects, such as face and speech recognition, image searching and classification, and automatic drive. Hence, CNN accelerators have become a trending research. Generally, Graphics processing units (GPUs) are widely applied in CNNaccelerators. However, Field-programmable gate arrays (FPGAs) have higher energy and resource efficiency compared with GPUs, moreover, high-level synthesis tools based on Open Computing Language (OpenCL) can reduce the verification and implementation period for FPGAs. In this project, PipeCNN[1] is implemented on Intel DE10-Standard FPGA. This OpenCL design acceleratesAlexnet through the interaction between Advanced RISC Machine (ARM) and FPGA. Then, PipeCNN optimization based on memory read and convolution is analyzed and discussed.