As environmental concerns and portability of electronic devices move to the forefront of priorities, innovative approaches which reduce processor energy consumption are sought. Approximate arithmetic units are one of the avenues whereby significant energy savings can be achieved. Approximation of fundamental arithmetic units is achieved by judiciously reducing the number of transistors in the circuit. A satisfactory tradeoff of energy vs. accuracy of the circuit can be determined by trial-and-error methods of each functional approximation. Although the accuracy of the output is compromised, it is only decreased to an acceptable extent that can still fulfill processing requirements. A number of scenarios are evaluated with approximate arithmetic units to thoroughly cross-check them with their accurate counterparts. Some of the attributes evaluated are energy consumption, delay and process variation. Additionally, novel methods to create such approximate units are developed. One such method developed uses a Genetic Algorithm (GA), which mimics the biologically-inspired evolutionary techniques to obtain an optimal solution. A GA employs genetic operators such as crossover and mutation to mix and match several different types of approximate adders to find the best possible combination of such units for a given input set. As the GA usually consumes a significant amount of time as the size of the input set increases, we tackled this problem by using various methods to parallelize the fitness computation process of the GA, which is the most compute intensive task. The parallelization improved the computation time from 2,250 seconds to 1,370 seconds for up to 8 threads, using both OpenMP and Intel TBB. Apart from using the GA with seeded multiple approximate units, other seeds such as basic logic gates with limited logic space were used to develop completely new multi-bit approximate adders with good fitness levels. iii The effect of process variation was also calculated. As the number of transistors is reduced, the distribution of the transistor widths and gate oxide may shift away from a Gaussian Curve. This result was demonstrated in different types of single-bit adders with the delay sigma increasing from 6psec to 12psec, and when the voltage is scaled to Near-Threshold-Voltage (NTV) levels sigma increases by up to 5psec. Approximate Arithmetic Units were not affected greatly by the change in distribution of the thickness of the gate oxide. Even when considering the 3-sigma value, the delay of an approximate adder remains below that of a precise adder with additional transistors. Additionally, it is demonstrated that the GA obtains innovative solutions to the appropriate combination of approximate arithmetic units, to achieve a good balance between energy savings and accuracy.

No description available.

A diminuição das dimensões do transistor MOS tem sido a principal estratégia adotada para alcançar otimizações de desempenho na fabricação de circuitos integrados. Contudo, reduzir as dimensões dos transistores tem se tornado uma tarefa cada vez mais difícil de ser alcançada. Nesse contexto, vários esforços estão sendo feitos para encontrar dispositivos alternativos que permitam futuros avanços em relação à capacidade computacional. Entre as mais promissoras tecnologias emergentes estão os transistores de efeito de campo com múltiplos e independentes gates (MIGFETs). MIGFETs são dispositivos controlados por mais que um terminal de controle permitindo que funções Booleanas com mais de uma variável sejam implementadas por um único dispositivo. Redes de chaves construídas com dispositivos MIGFET tendem a ser mais compactas do que as redes de chaves tradicionais. No entanto existe um compromisso em relação a redução no número de chaves, devido à maior capacidade lógica, e um maior tamanho e pior desempenho do dispositivo. Neste trabalho, pretendemos explorar tal balanceamento no sentido de avaliar os impactos do uso de MIGFETs na construção de circuitos integrados digitais. Dessa forma, alguns critérios de avaliação são apresentados no sentido de analisar área e atraso de circuitos construídos a partir de dispositivos MIGFET, onde cada transistor é representado por um modelo RC. Em particular, tal avaliação de área e desempenho é aplicada no projeto de circuitos somadores binários específicos (metodologia full-custom). Além do mais, bibliotecas de células construídas a partir de dispositivos MIGFET são utilizadas na síntese automática de circuitos de referência através da metodologia standard-cell. Através dos experimentos, é possível ter-se uma ideia, mesmo que inicial e pessimista, do quanto o layout de um dado MIGFET pode ser maior do que um single-gate FinFET e ainda apresentar redução na área do circuito devido à compactação lógica. / The scaling of MOS transistor has been the main manufacturing strategy for improving integrated circuit (IC) performance. However, as the device dimensions shrink, the scaling becomes harder to be achieved. In this context, much effort has been done in order to develop alternative devices that may allow further progress in computation capability. Among the promising emerging technologies is the multiple independent-gate field effect transistors (MIGFETs). MIGFETs are switch-based devices, which allow more logic capability in a single device. In general, switch networks built through MIGFET devices tend to be more compact than the traditional switch networks. However, there is a tradeoff between the number of logic switches merged and the area and performance of a given MIGFET. Thus, we aim to explore such a tradeoff in order to evaluate the MIGFET impacts in the building digital integrated circuits. To achieve this goal, in this work, we present an area and performance evaluation based on digital circuit built using MIGFET devices, where each MIGFET is represented through RC modelling. In particular, such an evaluation is applied on full-custom design of binary adder circuits and on standard-cell design flow targeting in a set of benchmark circuits. Through the experiments, it is possible have an insight, even superficial and pessimist, about how big can be the layout of a given MIGFET than the single-gate FinFET and still show a reduction in the final circuit area due to the logic compaction.

<p>För att snabba upp addering av tal, vilket är en vital del inom signalbehandling finns olika algoritmer. En sådan algoritm är Brent Kungs vilken har en tidsfördröjning proportionell mot log2(N). </p><p>I rapporten jämförs några olika varianter av adderare med avseende på grinddjup, vilket är proportionelltmot propageringstiden. En modulgenerator för Brent Kung-adderare implementeras med Skill-kod i Cadence. Modulgeneratorn kan genera adderare av obegränsad ordlängd och är även teknologi oberoende. Brent Kung-adderarens fysiska begränsningar studeras och förslag ges på lämpliga förbättringar.</p> / <p>To speed up the addition of numbers, which is a vital part of signal processing there are different types of algorithms. One of those algorithms is the Brent Kung-adder, which has a time delay proportional to log2(N). </p><p>In the report comparison of different adders has been done, taking into account grind-depth which is proportional to the propagation time. A module generator for the Brent Kung adder is implemented with skill-code in the program Cadence. The module generator can generate adders of infinite word length and is independent of the technology used. The physical limitations of Brent Kung adders are being studied and proposals for improvements are given in the report.</p>

<p>The phylogeography of a wide ranging temperate species, the adder, <i>Vipera berus</i>, was investigated using several genetic tools, with special emphasis on the post-glacial colonisation pattern of Fennoscandia. The area was colonised from two directions by adder populations representing different glacial refugia. The two populations meet in three places and the main contact zone is situated in Northern Finland. The two other contact zones are the result of dispersal across the Baltic Sea to the Umeå archepelago and South-Western Finland. Asymmetrically distributed nuclear genetic variation compared to mitochondrial DNA in the northern contact zone suggests a skewed gene flow from the east to the west across the zone. This pattern might reflect differences in dispersal among sexes and lineages, or may be accounted for by a selective advantage for nuclear variation of eastern origin among Fennoscandian adders.</p><p>The phylogeographic pattern for adders across the entire species range was addressed by sequencing part of the mitochondrial genome and scoring microsatellite markers. The adder can be divided into three major genetic groups. One group is confined to the Balkan peninsula harbouring the distribution range of <i>V. b. bosniensis</i>. A second, well differentiated group is restricted to the Southern Alps. These two areas have probably served as refugia for adders during a number of ice ages for the adders. The third group is distributed across the remainder of the species’ range, from extreme Western Europe to Pacific Russia and can be further divided into one ancestral group inhabiting the Carpathians refugial area, and three more recent groups inhabiting areas west, north and east of the Alps. The adder provides an example of a species where the Mediterranean areas are housing endemic populations, rather than the sources for post-glacial continental colonisation. Continent-wide colonisation has instead occurred from up to three cryptic northern refugia. </p>

The phylogeography of a wide ranging temperate species, the adder, Vipera berus, was investigated using several genetic tools, with special emphasis on the post-glacial colonisation pattern of Fennoscandia. The area was colonised from two directions by adder populations representing different glacial refugia. The two populations meet in three places and the main contact zone is situated in Northern Finland. The two other contact zones are the result of dispersal across the Baltic Sea to the Umeå archepelago and South-Western Finland. Asymmetrically distributed nuclear genetic variation compared to mitochondrial DNA in the northern contact zone suggests a skewed gene flow from the east to the west across the zone. This pattern might reflect differences in dispersal among sexes and lineages, or may be accounted for by a selective advantage for nuclear variation of eastern origin among Fennoscandian adders. The phylogeographic pattern for adders across the entire species range was addressed by sequencing part of the mitochondrial genome and scoring microsatellite markers. The adder can be divided into three major genetic groups. One group is confined to the Balkan peninsula harbouring the distribution range of V. b. bosniensis. A second, well differentiated group is restricted to the Southern Alps. These two areas have probably served as refugia for adders during a number of ice ages for the adders. The third group is distributed across the remainder of the species’ range, from extreme Western Europe to Pacific Russia and can be further divided into one ancestral group inhabiting the Carpathians refugial area, and three more recent groups inhabiting areas west, north and east of the Alps. The adder provides an example of a species where the Mediterranean areas are housing endemic populations, rather than the sources for post-glacial continental colonisation. Continent-wide colonisation has instead occurred from up to three cryptic northern refugia.

Achieving high performance is one of the most difficult challenges in designing digital circuits. Flip-flops and adders are key blocks in most digital systems and must therefore be designed to yield highest performance. In this thesis, a new high performance serial adder is developed while power consumption is attained. Also, a statistical framework for the design of flip-flops is introduced that ensures that such sequential circuits meet timing yield under performance criteria. Firstly, a high performance serial adder is developed. The new adder is based on the idea of having a constant delay for the addition of two operands. While conventional adders exhibit logarithmic delay, the proposed adder works at a constant delay order. In addition, the new adder's hardware complexity is in a linear order with the word length, which consequently exhibits less area and power consumption as compared to conventional high performance adders. The thesis demonstrates the underlying algorithm used for the new adder and followed by simulation results. Secondly, this thesis presents a statistical framework for the design of flip-flops under process variations in order to maximize their timing yield. In nanometer CMOS technologies, process variations significantly impact the timing performance of sequential circuits which may eventually cause their malfunction. Therefore, developing a framework for designing such circuits is inevitable. Our framework generates the values of the nominal design parameters; i.e., the size of gates and transmission gates of flip-flop such that maximum timing yield is achieved for flip-flops. While previous works focused on improving the yield of flip-flops, less research was done to improve the timing yield in the presence of process variations.

För att snabba upp addering av tal, vilket är en vital del inom signalbehandling finns olika algoritmer. En sådan algoritm är Brent Kungs vilken har en tidsfördröjning proportionell mot log2(N). I rapporten jämförs några olika varianter av adderare med avseende på grinddjup, vilket är proportionelltmot propageringstiden. En modulgenerator för Brent Kung-adderare implementeras med Skill-kod i Cadence. Modulgeneratorn kan genera adderare av obegränsad ordlängd och är även teknologi oberoende. Brent Kung-adderarens fysiska begränsningar studeras och förslag ges på lämpliga förbättringar. / To speed up the addition of numbers, which is a vital part of signal processing there are different types of algorithms. One of those algorithms is the Brent Kung-adder, which has a time delay proportional to log2(N). In the report comparison of different adders has been done, taking into account grind-depth which is proportional to the propagation time. A module generator for the Brent Kung adder is implemented with skill-code in the program Cadence. The module generator can generate adders of infinite word length and is independent of the technology used. The physical limitations of Brent Kung adders are being studied and proposals for improvements are given in the report.

Achieving high performance is one of the most difficult challenges in designing digital circuits. Flip-flops and adders are key blocks in most digital systems and must therefore be designed to yield highest performance. In this thesis, a new high performance serial adder is developed while power consumption is attained. Also, a statistical framework for the design of flip-flops is introduced that ensures that such sequential circuits meet timing yield under performance criteria. Firstly, a high performance serial adder is developed. The new adder is based on the idea of having a constant delay for the addition of two operands. While conventional adders exhibit logarithmic delay, the proposed adder works at a constant delay order. In addition, the new adder's hardware complexity is in a linear order with the word length, which consequently exhibits less area and power consumption as compared to conventional high performance adders. The thesis demonstrates the underlying algorithm used for the new adder and followed by simulation results. Secondly, this thesis presents a statistical framework for the design of flip-flops under process variations in order to maximize their timing yield. In nanometer CMOS technologies, process variations significantly impact the timing performance of sequential circuits which may eventually cause their malfunction. Therefore, developing a framework for designing such circuits is inevitable. Our framework generates the values of the nominal design parameters; i.e., the size of gates and transmission gates of flip-flop such that maximum timing yield is achieved for flip-flops. While previous works focused on improving the yield of flip-flops, less research was done to improve the timing yield in the presence of process variations.

This thesis focuses on the logical design of binary adders. It covers topics extending from cardinal numbers to carry skip optimization. The conventional adder designs are described in detail, including: carry completion, ripple carry, carry select, carry skip, conditional sum, and carry lookahead. We show that the method of parallel prefix analysis can be used to unify the conventional adder designs under one parameterized model. The parallel prefix model also produces other useful configurations, and can be used with carry operator variations that are associative. Parallel prefix adder parameters include group sizes, tree shape, and device sizes. We also introduce a general algorithm for group size optimization. Code for this algorithm is available on the World Wide Web. Finally, the thesis shows the derivation for some carry operator variations including those originally given by Majerski and Ling. / text