This dissertation is aimed at the development of a current mode instrumentation amplifier (CMIA) with a high common mode input range. This characteristic is obtained due to the rail-to-rail operational amplifiers (opamps). These opamps are built with rail-to-rail differential amplifiers as input stages, and with cascode-based output stages, which are able to copy its current by adding identical branches and connecting their gates without the voltage degradation as the known CMIA topologies. The main contribution of this work is the development of a rail-to-rail current mode instrumentation amplifier, analyzing the pros and cons of this topology. The functionality of the proposed topology is shown through measured results of a manufactured integrated circuit. This first prototype, although it was operated in a large input common mode range, presented insufficient values of CMRR (Common Mode Rejection Ratio) and VOS (Offset voltage). These two characteristics were studied and modeled, the instrumentation amplifier was re-designed, and simulated results demonstrate important improvements. / Esta dissertação tem como objetivo o desenvolvimento de um amplificador de instrumentação em modo corrente com uma ampla faixa de entrada em modo comum. Esta característica é obtida graças ao emprego de estágios de amplificação rail-to-rail na entrada e a geração do sinal de saída através do espelhamento da corrente diretamente dos gates dos transistores do estágio ao invés da alternativa clássica, onde espelhos são ligados em série e degradam a excursão do sinal de saída. Com esta proposta, é possível a implementação de ampops com entrada e saída rail-to-rail. A principal contribuição deste trabalho é analisar as vantagens e desvantagens da utilização destas soluções na implementação de um amplificador de instrumentação com entrada rail-to-rail. A funcionalidade da topologia proposta é demonstrada através dos resultados medidos de um circuito integrado fabricado. Este primeiro protótipo, apesar do bom funcionamento em toda a faixa de entrada em modo comum, apresentou valores insatisfatórios de CMRR (Common Mode Rejection Ratio) e de VOS (Tensão de offset), o que levou a um aprofundamento no estudo e modelagem destas características. A partir disto, o circuito foi re-projetado e os resultados de simulação demonstram melhorias bastante significativas em suas características.

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

L'environnement radiatif spatial est composé d'une grande diversité de particules dans un spectre en énergie très large. Parmi les effets affectant les composants électroniques, on distingue les effets cumulatifs et les effets singuliers transitoires analogiques (ASET). Les effets cumulatifs correspondent à une dégradation continue des paramètres électriques du composant induits par un dépôt d'énergie à faible débit de dose tout au long de la mission spatiale. Les ASETs sont eux causés par le passage d'une particule unique traversant une zone sensible du composant et engendrant une impulsion de tension transitoire qui se propage à la sortie de l'application. Au cours des tests au sol, les deux effets sont étudiés séparément, mais ils se produisent simultanément en vol. Il se produit donc un effet de synergie, induit par la combinaison de la dose et de l'apparition soudaine d'un ASET dans le dispositif préalablement irradié.Une étude de l'effet de synergie dose-ASET est proposée. Pour accélérer les irradiations, une technique connue sous le nom de « méthode de commutation de débit de dose » (DRS) prenant en compte la sensibilité accrue au faible débit de dose (ELDRS) est utilisée. Un modèle haut niveau est développé en utilisant l'analyse circuit permettant de prédire l'effet de synergie observé sur un amplificateur opérationnel à trois étages. Pour prédire l'effet de synergie, l'effet de dose est pris en compte en faisant varier les paramètres décrivant le modèle suivant une loi de variation déduite de la dégradation du courant d'alimentation qui est couramment enregistré au cours des essais industriels. Enfin, les effets transitoires des radiations sur l'électronique (TREEs) induits par un environnement de très fort débit de dose de rayons X pulsés ainsi que l'effet de synergie dose-TREE sont étudiés à l'aide d'un générateur de Flash-X. La méthode classique d'analyse des ASETs permet alors d'expliquer la forme des impulsions transitoires observées. / The natural radiative space environment is composed by numerously particles in a very large energy spectrum. From an electronics component point of view, it is possible to distinguish cumulative effects and so-called Analog Single Event Transient effects (ASET). Cumulative effects correspond to continuous deterioration of the electrical parameters of the component, due to a low dose rate energy deposition (Total Ionizing Dose: TID) throughout the space mission. ASETs are caused by a single energetic particle crossing a sensitive area of the component inducing a transient voltage pulse that occurs at the output of the application. During ground testing, both effects are studied separately but happen simultaneously in flight. As a result a synergy effect, induced by the combination of the low dose rate energy deposition and the sudden occurrence of an ASET in the device previously irradiated, occurs. A study of dose-ASET synergistic effects is proposed using an accelerated irradiation test technique known as Dose Rate Switching method (DRS) tacking into account the concern of the Enhanced Low Dose Rate Sensitivity (ELDRS). A High Level Model is developed using circuit analysis to predict the synergy effect observed on a three stages operational amplifier. To predict synergy effect, the TID effect is taken into account by varying the model parameters following a variation law deduced from the degradation of the supply current which recorded during usual industrial TID testing. Finally, the Transient Radiation Effects on Electronics (TREE) phenomena induced by a Very High Dose Rate X-ray pulse environment and the dose-TREE synergy effect are then investigated using an X-ray flash facility. The classical ASETs methodology analysis can explain the shapes of transients observed.