A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009 / Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento. / Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Αντικείμενο της διπλωματικής εργασίας είναι η σχεδίαση ενός βιοϊατρικού συστήματος που είναι κατάλληλο για την ανίχνευση εμβοών σε ασθενείς. Το σύστημα αυτό αποτελείται από ένα αναλογικό τμήμα το οποίο περιλαμβάνει τους εξαγωγείς ενέργειας ζώνης συχνοτήτων για τα alpha, gamma και theta waves του εγκεφάλου που τροφοδοτούν τα αντίστοιχα κανάλια του συστήματος. Επίσης, το σύστημα περιλαμβάνει και ένα ψηφιακό τμήμα αποτελούμενο από συγκριτές ρεύματος και μια πύλη AND και το οποίο θα χρησιμεύσει για την λήψη της απόφασης σχετικά με το αν πάσχει ή όχι ο ασθενής. Η έξοδος του συστήματος θα οδηγεί ένα σύστημα ανάδρασης, ο οποίος θα προσαρμόζει τα επίπεδα έντασης των αντίστοιχων σημάτων που δέχεται ο ασθενής για την αποφυγή της εμφάνισης του φαινομένου της εμβοής. Η υλοποίηση του συστήματος γίνεται με χρήση MOS transistors τα οποία λειτουργούν στην περιοχή υποκατωφλίου. Η χρήση μικρών ρευμάτων πόλωσης δίνει τη δυνατότητα για σχεδίαση συστημάτων με χαμηλή κατανάλωση ισχύος και ταυτόχρονα επιτρέπει την υλοποίηση μεγάλων τιμών αντιστάσεων, οι οποίες είναι απαραίτητες για την πραγματοποίηση μεγάλων σταθερών χρόνου που απαιτούνται για τη διαχείριση των χαμηλής συχνότητας βιοϊατρικών σημάτων. Στόχος της διπλωματικής εργασίας είναι η ανάπτυξη πρωτότυπης τοπολογίας για το αναλογικό τμήμα του συστήματος. Αυτό επιτεύχθηκε με την ανάπτυξη νέων δομών φίλτρων τα οποία λειτουργούν στο πεδίο του υπερβολικού ημιτόνου. Οι κύριοι λόγοι υιοθέτησης αυτής της τεχνικής είναι ότι προσφέρει ταυτόχρονα τα παρακάτω: (α) δυνατότητα επεξεργασίας σημάτων τα οποία είναι μεγαλύτερα από το ρεύμα πόλωσης, λόγω της ενσωματωμένης λειτουργίας σε τάξη-ΑΒ, (β) δυνατότητα λειτουργίας με καλή γραμμικότητα σε πολύ χαμηλή τάση τροφοδοσίας, (γ) ηλεκτρονική ρύθμιση των συχνοτικών χαρακτηριστικών τους από το ρεύμα πόλωσης, (δ) υλοποίηση φίλτρων χωρίς αντιστάτες, (ε) υλοποίηση φίλτρων με χρήση μόνο γειωμένων πυκνωτών. Η σχεδίαση των κυκλωμάτων, τόσο σε επίπεδο σχηματικού, όσο και σε επίπεδο μασκών, έγινε με τη χρήση του λογισμικού Cadence και με το Design Kit που παρέχεται από την τεχνολογία AMS CMOS C35 0.35μm. Συγκρινόμενη με την αντίστοιχη ήδη προταθείσα δομή ανιχνευτή εμβοών, η προτεινόμενη τοπολογία προσφέρει τα παρακάτω ελκυστικά χαρακτηριστικά: (α) μειωμένη κατανάλωση ισχύος και (β) λειτουργία του αναλογικού τμήματος σε μικρότερη τάση τροφοδοσίας (0.5V). / Subject of this M. Sc.Τhesis is the design of a biomedical system that is suitable for detecting tinnitus in patients. This system consists of an analog subsystem comprising band energy extractors for alpha, gamma and theta waves of the EEG that feed the channels of the system. The system also includes a digital section composed of current comparator and AND gate, which will serve as a decision on whether or not the suffering patient. The output of the system will drive a feedback system, which will adjust the intensity levels of the respective signals received by the patient to prevent the occurrence of the phenomenon of tinnitus. The system implementation is done using MOS transistors operating in the subthreshold region. The use of low-level bias currents allows for system design with low power consumption and, simultaneously, enables the implementation of large values of resistors that are necessary for the realization of large time constants required for the handling of low frequency biomedical signals. The aim of this thesis is to develop novel topology for the analog subsystem. Tjhis was achieved through the development ddevelopment of novel structures of filters using the concept of filtering in the Sinh-Domain. The main reasons for using this technique is that it simultaneously offers the following attractive characteristics: (a) capability for processing signals which are larger than the bias current, due to the inherent class-AB operation, (b) ability to achieve a relative high linearity at very low power supply voltage, (c) electronic adjustment of frequency characteristics through the bias current, (d) implementation of filters without resistors, and (e) implementation of filters using only grounded capacitors. The design of circuits, both at schematic and post-layout levels was performed using the Cadence software and the Design Kit provided by the AMS CMOS C35 0.35μm technology. Compared with the corresponding already proposed structure tinnitus detector, the proposed topology to offer the following attractive features: (a) reduced power consumption, and (b) operation of the analog section in lower supply voltage (0.5V).

Τα αναλογικά φίλτρα στο πεδίο του υπερβολικού ημιτόνου (Sinh-Domain filters) είναι μια οικογένεια φίλτρων συνεχούς χρόνου στην οποία γίνεται χρήση της Ι/V χαρακτηριστικής των ενεργών στοιχείων (BJT τρανζίστορ) για να επιτευχτεί γραμμική συμπεριφορά από είσοδο σε έξοδο. Τα Sinh-Domain φίλτρα συμπίεσης/αποσυμπιέσης προσφέρουν πλεονεκτήματα, όπως την ηλεκτρονική ρύθμιση, τη δυνατότητα λειτουργίας σε χαμηλή τάση τροφοδοσίας και τη λειτουργία σε υψηλές συχνότητες. Στη παρούσα Μεταπτυχιακή Διπλωματική Εργασία προτείνεται μια νέα μέθοδος σχεδίασης Sinh-domain φίλτρων που στηρίζεται στη κυματική μέθοδο. Αρχικά αναπτύσσονται τα κυματικά ισοδύναμα των παθητικών στοιχείων στο πεδίο του υπερβολικού ημιτόνου χρησιμοποιώντας μια κοινή έως σήμερα λογική σχεδίασης η οποία έχει χρησιμοποιηθεί στη σχεδίαση κυματικών φίλτρων τόσο στο λογαριθμικό πεδίο (Log-Domain) όσο και στο πεδίο της τετραγωνικής ρίζας (Square Root-Domain). Έπειτα γίνεται χρήση των κυματικών ισοδυνάμων που πρόεκυψαν για να σχεδιαστούν ηλεκτρονικά φίλτρα τρίτης τάξης, των οποίων η λειτουργία εξομοιώνεται μέσω του Analog Design Environment του λογισμικού Cadence και με χρήση των μοντέλων των MOS transistor που παρέχονται από την τεχνολογία AMS 0.35μm. Στη συνέχεια προτείνεται μια νέα βελτιωμένη εκδοχή των κυματικών ισοδυνάμων πρώτης και δεύτερης τάξης στο πεδίο του υπερβολικού ημιτόνου. Τα βελτιωμένα κυματικά ισοδύναμα στηρίζονται σε μια νέα λογική σχεδίασης η οποία σκοπεύει στη μείωση των απαιτούμενων ενεργών στοιχείων και ως εκ τούτου στη μείωση της καταναλισκόμενης ισχύος αλλά και στη προσθήκη της δυνατότητας εξωτερικά ελεγχόμενου προγραμματισμού της ηλεκτρονικής συμπεριφοράς των νέων κυματικών δίθυρων. Ακολουθεί ο σχεδιασμός ηλεκτρονικών φίλτρων χρησιμοποιώντας αυτή τη φορά τη νέα βελτιωμένη εκδοχή των κυματικών διθύρων και η εξομοίωση της λειτουργίας αυτών με το Analog Design Environment του λογισμικού Cadence. Τέλος πραγματοποιείται συγκριτική μελέτη μεταξύ φίλτρων που σχεδιάστηκαν χρησιμοποιώντας την απλή και τη βελτιωμένη εκδοχή των κυματικών διθύρων σκοπό να διαπιστωθεί ο βαθμός βελτίωσης που επιτυγχάνεται. / Sinh-Domain companding filters are a family of continuous time filters that instead of being designed using locally linearized components, directly exploit the non-linear nature of a BJT transistor, in forward active region or MOS transistor in weak inversion in order to obtain a system with overall linear performance. This way they, exhibit high linearity even for large signal to bias ratios. In addition, they have some other interesting features like tunability, resistorless realizations and capability of operating under low power supply voltage. In this Master Thesis it is proposed a new method of designing Sinh-Domain filters which is based on the wave method. Initially the wave equivalents of passive components in the Sinh-Domain have been introduced, using the conventional approach as in the case of Log Domain and Square Root Domain filters. As design examples, low pass ,band pass and high pass filters have been designed and their performance have been evaluated using the Analog Design Environment of the Cadence software.MOS and Bipolar transistors models provided by AMS 0.35μm. BiCmos technology have been employed in simulation. Later, it is proposed a new improved version of wave equivalents of first and second order in the Sinh-Domain. This offer the following benefits: a)reduced active element count and hence reduced power consumption and b) capability of externally controlled programming for obtaining all the equivalents from the same core. As design examples, low pass, band pass and high pass filters have been designed and their performance have been evaluated using the Analog Design Environment of the Cadence software As a final step a performance among the proposed filter topologies has been performed in order to be evident the attractive characteristics offered by the proposed wave equivalents.

Η παρούσα Διπλωματική Εργασία εστίασε το ενδιαφέρον της στην ανίχνευση του QRS συμπλέγματος στα ηλεκτροκαρδιογραφήματα με σκοπό τον εντοπισμό χρόνιων ή μη παθήσεων της ανθρώπινης καρδιάς. Το σύστημα αυτό αποτελείται από ένα ζωνοπερατό φίλτρο 2ης-τάξης, ένα διαφοριστή, έναν τετραγωνιστή και ένα βαθυπερατό φίλτρο 1ης-τάξης. Η υλοποίηση του συστήματος γίνεται με χρήση MOS transistor τα οποία λειτουργούν στην περιοχή υποκατωφλίου. Η χρήση μικρών ρευμάτων πόλωσης επιτρέπει τη σχεδίαση συστημάτων με χαμηλή κατανάλωση ισχύος και ταυτόχρονα την υλοποίηση μεγάλων τιμών αντιστάσεων, οι οποίες είναι απαραίτητες για την πραγματοποίηση μεγάλων σταθερών χρόνου, που απαιτούνται για τη διαχείριση των χαμηλής συχνότητας βιοϊατρικών σημάτων. Στόχος της Διπλωματικής Εργασίας είναι η ανάπτυξη τοπολογίας για το αναλογικό τμήμα του συστήματος. Για το σκοπό αυτό προτείνεται η συστηματική σχεδίαση φίλτρων υψηλής τάξης στο πεδίο του υπερβολικού ημιτόνου, με χρήση ήδη υπαρχόντων μη-γραμμικών διαγωγών υπερβολικού ημιτόνου, συνημίτονου. Η συμπίεση-αποσυμπίεση του προς επεξεργασία σήματος επιτυγχάνεται με την κατάλληλη τοποθέτηση συμπληρωματικών τελεστών ενώ ταυτόχρονα διατηρείται γραμμική η συνολική συμπεριφορά των διατάξεων. Η εφαρμογή της μεθόδου του κατωφλίου, ωστόσο, αλλά και η επαλήθευση της λειτουργίας του αναλογικού μέρους, πραγματοποιήθηκε με τη χρήση του λογισμικού Matlab. Η σχεδίαση των κυκλωμάτων σε όλα τα επίπεδα ιεραρχίας πραγματοποιήθηκε με τη χρήση του λογισμικού Cadence και με το Design Kit που παρέχεται από την τεχνολογία AMS CMOS C35 0.35μm. / This M.Sc. Thesis focused on proper detection of QRS complex on electrocardiograms to identify chronic or non-chronic diseases of human heart. This system consists of a 2nd-order bandpass filter, a differentiator, a squarer and a 1st-order low-pass filter. The system implementation is using MOS transistors operating in the subthreshold region. The use of low-level bias currents allows the design of systems with low power consumption and simultaneously implementing large resistance values , which are necessary for the realization of large time constants required for the management of low frequency biomedical signals. The aim of this thesis is to develop topology for the analog subsystem. For this purpose a systematic design of high order filters in the field of Sinh-Domain , using existing trims nonlinear hyperbolic sine and cosine. The compression - expansion of the signal to be processed is achieved by proper placement of additional constants while maintaining the total linear behavior of the devices. The application of the threshold, however, but also to verify the operation of the analog part , performed using the software Matlab. The design of circuits at all levels of hierarchy was performed using the software Cadence and the Design Kit provided by technology AMS CMOS C35 0.35μm.

Οι μετατροπείς της ενεργούς τιμής σήματος σε συνεχές είναι βαθμίδες με ευρεία εφαρμογή σε τηλεπικοινωνιακά συστήματα και σε βιοϊατρικά συστήματα. Στην εργασία αυτή, προτείνεται μια νέα γενική τοπολογία μετατροπέα ενεργούς τιμής σήματος σε συνεχές, η οποία λειτουργεί στο πεδίο του υπερβολικού ημιτόνου. Κύρια πλεονεκτήματα είναι η δυνατότητα λειτουργίας σε περιβάλλον χαμηλής τάσης τροφοδοσίας και η δυνατότητα επεξεργασίας σημάτων πολύ μεγαλύτερων της πόλωσης. Η εξομοίωση της λειτουργίας του κυκλώματος έγινε με τη χρήση του λογισμικού Analog Design Environment της Cadence. / Rms to DC converters, are stages with wide range of applications in telecommunication and biomedical systems. In this project, a new rms to dc converter topology is proposed, operating in sinh domain. Main advantages are the ability to operate in low voltage and the ability to process signals larger than bias. The circuit was simulated using Cadence Analog Design Environment software.

Οι ηλεκτρονικοί αρμονικοί ταλαντωτές είναι βαθμίδες με ευρεία εφαρμογή σε τηλεπικοινωνιακά συστήματα, σε συστήματα επεξεργασίας σήματος και σε ηλεκτρονικά ισχύος. Στην εργασία αυτή, προτείνεται μια νέα γενική τοπολογία ταλαντωτή πολλαπλών φάσεων, η οποία λειτουργεί στο πεδίο του υπερβολικού ημιτόνου. Κύρια πλεονεκτήματα είναι η δυνατότητα λειτουργίας σε περιβάλλον χαμηλής τάσης τροφοδοσίας και η ηλεκτρονική ρύθμιση της συμπεριφοράς του ταλαντωτή. Ως παράδειγμα σχεδίασης δίνεται ένας αρμονικός ταλαντωτής πολλαπλών φάσεων εξόδου 3ης/6ης τάξης, που η εξομοίωση της λειτουργίας του έγινε με τη χρήση του λογισμικού Analog Design Environment της Cadence. / Electronic harmonic oscillators are stages with wide application in telecommunication systems, in signal processing systems and power electronics. In this project, a new multiphase oscillator topology is proposed, designed to operate in sinh domain. Main advantages are the ability to operate at low voltage and the electronic tuning of the oscillator’s behavior. A multiphase sinusoidal oscillator, 3rd/6th order, is given as an example. The validity of the proposed methods is verified through simulation results using the Cadence Analog Design Environment software.

Αντικείμενο της παρούσας Διπλωματικής Εργασίας είναι η σχεδίαση ενός ενισχυτή χαμηλής τάσης τροφοδοσίας για την ανίχνευση καρδιακών σημάτων σε βηματοδότες. Οι επιταγές της σύγχρονης τεχνολογίας για τα ολοκληρωμένα κυκλώματα είναι η χαμηλή κατανάλωση ισχύος, η χρήση χαμηλής τάσης τροφοδοσίας, η μείωση του κόστους παραγωγής, οι όλο και μικρότερες διαστάσεις των transistors και ταυτόχρονα υψηλές επιδόσεις. Η χρήση όμως της χαμηλής τάσης τροφοδοσίας αποτελεί πρόκληση από σχεδιαστικής άποψης, για την ταυτόχρονη μείωση της κατανάλωσης ισχύος χωρίς να υποβαθμίζεται η ποιότητα του σήματος. Αυτό το πρόβλημα λύνουν μέθοδοι όπως η σχεδίαση στο πεδίο του λογαρίθμου. Τα συστήματα στο πεδίο του λογαρίθμου (Log-Domain systems) αποτελούν υποκατηγορία των συστημάτων συμπίεσης – αποσυμπίεσης (companding systems) και ανήκουν στα ELIN (Externally Linear Internaly Non-linear) συστήματα. Τα πλεονεκτήματα των συστημάτων στο πεδίο του λογαρίθμου είναι η μεγάλη δυναμική περιοχή (Dynamic Range), η δυνατότητα επεξεργασίας μεγάλων σημάτων (large signal), καθώς και η λειτουργία σε περιβάλλον χαμηλής τροφοδοσίας. Υλοποιώντας φίλτρα στο πεδίο του λογαρίθμου προσφέρονται ελκυστικά χαρακτηριστικά όπως η ηλεκτρονική ρύθμιση της συχνότητας αποκοπής ή κεντρικής συχνότητας (electronic tuning) και η σχεδίαση χωρίς παθητικές αντιστάσεις (resistorless realization). Η καρδιά είναι ένα περίπλοκο σύστημα το οποίο φροντίζει για την κυκλοφορία του αίματος στο σώμα. Το έναυσμα για την εκκίνηση κάθε καρδιακού κύκλου προέρχεται από ένα ηλεκτρικό σήμα το οποίο ξεκινάει από το φλεβοκόμβο και διαδίδεται στο υπόλοιπο μυοκάρδιο, για να ξεκινήσει ένας νέος καρδιακός κύκλος. Σε ορισμένες περιπτώσεις η καρδιά δεν λειτουργεί σωστά και το ρόλο του φλεβοκόμβου έρχεται να καλύψει το ηλεκτρονικό σύστημα του βηματοδότη, το οποίο ανιχνεύει το καρδιακό σήμα και όταν κριθεί απαραίτητο εφαρμόζει την κατάλληλη θεραπεία με ηλεκτρικές ώσεις. Για την βελτίωση της ποιότητας ζωής ασθενών με καρδιακά προβλήματα ένας βηματοδότης πρέπει να έχει όσο δυνατόν μικρότερο μέγεθος και μεγαλύτερη αυτονομία. Η πρόοδος της τεχνολογίας αποζητά τη σχεδίαση ενός συστήματος ενισχυτή για την ανίχνευση καρδιακών σημάτων πλέον ικανό να ανταπεξέλθει στη χαμηλή τάση τροφοδοσίας και να έχει μεγάλη αυτονομία λειτουργίας για την εισαγωγή του π.χ. σε ένα βηματοδότη. Το σύστημα που προτείνεται σε αυτή τη Διπλωματική Εργασία έχει ως σκοπό να εκπληρώσει τις ανάγκες αυτές χρησιμοποιώντας κυκλώματα τα οποία μπορούν να λειτουργήσουν σε χαμηλή τάση τροφοδοσίας και ταυτόχρονα να μειώνουν την κατανάλωση ισχύος. Η υλοποίηση των κυκλωμάτων μόνο με CMOS transistors στην περιοχή υποκατωφλίου, εκτός του γεγονότος ότι μειώνει το κόστος παραγωγής καθώς δεν χρησιμοποιούνται BJT transistors, προσφέρει λόγω της τεχνικής σχεδίασης στο πεδίο του λογαρίθμου και μεγάλη δυναμική περιοχή. Για την τεχνολογία 0.35μm της AMS επιτυγχάνεται λειτουργία σε περιβάλλον με 0.5V τάση τροφοδοσίας και κατανάλωση ισχύος της τάξης των 2.92nW. Ο ενισχυτής για την ανίχνευση καρδιακών σημάτων που προτείνεται, περιλαμβάνει ένα ζωνοπερατό φίλτρο σχεδιασμένο στο πεδίο του λογαρίθμου και τα κυκλώματα απόλυτης τιμής, μετατροπής της ενεργής τιμής σήματος σε σταθερό ρεύμα και συγκριτή ρεύματος. / This M.Sc Thesis deals with the design of a low voltage cardiac sense amplifier for pacemakers. The demands of modern technology for integrated circuits are low power consumption, ultra low power supply voltage, reduction of the production cost and high performance. Due to the fact that the use of low power supply voltage is a design challenge, the employment of the Log-Domain filter technique is an attractive solution for realizing high-performance analog processing systems. Log-Domain systems are a sub-category of compading (compressing/expanding) systems and belong to ELIN (Externally Linear Internaly Non-linear) systems. The advantages of Log-Domain systems are large dynamic range, handling of signals with relatively large amplitude, realization in a low-voltage environment, electronic tuning of their frequency characteristics and resistorless realizations. The heart is a complex system that takes care of blood circulation for the whole body. The trigger to commence the cardiac cycle is an electric signal which starts from the sinus node and expands to the rest of the myocardium in order for a new cardiac cycle to set off. In some cases, the heart does not function properly and the role of the sinus node is taken by a pacemaker, who senses the cardiac signal and when it is judged, it cures the problem with an electric pulse. In order to improve the patient’s quality of life a pacemaker has to be small in size and a prolonged battery life. Technological evolution and market demands have led to a demand for a design of a cardiac sense amplifier capable of coping with low power supply voltage and long battery life. The proposed system of this M.Sc thesis is meant to fulfill these needs by using circuits capable of functioning in a low power supply voltage environment as well as reducing power consumption. Implementing those circuits solely with CMOS transistors in the sub -threshold region, not only does it reduce the production cost since no BJT transistors are used but also it offers a large dynamic range due to the design of the circuits. For the AMS 0.35μ CMOS process of by the system functions for a power supply voltage of 0.5V while it dissipates 2.92nW. The proposed cardiac sense amplifier consists of a bandpass Log-Domain filter and circuits like an absolute value circuit, an rms-dc current converter circuit and a current comparator, which were carefully designed in order to follow the demands of modern technology and achieve the goal of low power dissipation.

La Non-Linéarité-Différentielle (NLD) et la Non-Linéarité-Intégrale (NLI) sont les performances statiques les plus importantes des Convertisseurs Analogique-Numérique (CAN) qui sont mesurées lors d’un test de production. Ces deux performances indiquent la déviation de la fonction de transfert du CAN par rapport au cas idéal. Elles sont obtenues en appliquant une rampe ou une sinusoïde lente au CAN et en calculant le nombre d’occurrences de chacun des codes du CAN.Ceci permet la construction de l’histogramme qui permet l’extraction de la NLD et la NLI. Cette approche requiert lacollection d’une quantité importante de données puisque chacun des codes doit être traversé plusieurs fois afin de moyenner le bruit et la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. En effet,malgré que les circuits analogiques et mixtes occupent une surface qui n’excède pas généralement 5% de la surface globald’un System-on-Chip (SoC), leur temps de test représente souvent plus que 30% du temps de test global. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d’attention et qui est en train deprendre de l’ampleur. Les CAN de type pipeline offrent un bon compromis entre la vitesse, la résolution et la consommation.Ils sont convenables pour une variété d’applications et sont typiquement utilisés dans les SoCs destinés à des applicationsvidéo. En raison de leur façon particulière du traitement du signal d’entrée, les CAN de type pipeline ont des codes de sortiequi ont la même largeur. Par conséquent, au lieu de considérer tous les codes lors du test, il est possible de se limiter à un sous-ensemble, ce qui permet de réduire considérablement le temps de test. Dans ce travail, une technique pour l’applicationdu test à code réduit pour les CANs de type pipeline est proposée. Elle exploite principalement deux propriétés de ce type deCAN et permet d’obtenir une très bonne estimation des performances statiques. La technique est validée expérimentalementsur un CAN 11-bit, 55nm de STMicroelectronics, obtenant une estimation de la NLD et de la NLI pratiquement identiques àla NLD et la NLI obtenues par la méthode classique d’histogramme, en utilisant la mesure de seulement 6% des codes. / Differential Non Linearity (DNL) and Integral Non Linearity (INL) are the two main static performances ofAnalog to-Digital Converters (ADCs) typically measured during production testing. These two performances reflect thedeviation of the transfer curve of the ADC from its ideal form. In a classic testing scheme, a saturated sine-wave or ramp isapplied to the ADC and the number of occurrences of each code is obtained to construct the histogram from which DNL andINL can be readily calculated. This standard approach requires the collection of a large volume of data because each codeneeds to be traversed many times to average noise. Furthermore, the volume of data increases exponentially with theresolution of the ADC under test. According to recently published data, testing the mixed-signal functions (e.g. dataconverters and phase locked loops) of a System-on-Chip (SoC) contributes to more than 30% of the total test time, althoughmixed-signal circuits occupy a small fraction of the SoC area that typically does not exceed 5%. Thus, reducing test time forADCs is an area of industry focus and innovation. Pipeline ADCs offer a good compromise between speed, resolution, andpower consumption. They are well-suited for a variety of applications and are typically present in SoCs intended for videoapplications. By virtue of their operation, pipeline ADCs have groups of output codes which have the same width. Thus,instead of considering all the codes in the testing procedure, we can consider measuring only one code out of each group,thus reducing significantly the static test time. In this work, a technique for efficiently applying reduced code testing onpipeline ADCs is proposed. It exploits two main properties of the pipeline ADC architecture and allows obtaining an accurateestimation of the static performances. The technique is validated on an experimental 11-bit, 55nm pipeline ADC fromSTMicroelectronics, resulting in estimated DNL and INL that are practically indistinguishable from DNL and INL that areobtained with the standard histogram technique, while measuring only 6% of the codes.