abstract: In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta modulator employing a cascade of integrators with feed forward (CIFF) architecture in a single feedback loop topology is used for implementing the ADC. In order to enable operation in the intended application environments, an RC time constant tuning engine is proposed. The tuning engine is used to maintain linearity of a 10 ksps 20 bit continuous time sigma delta ADC designed for spectroscopy applications in space. The proposed circuit which is based on master slave architecture automatically selects on chip resistors to control RC time constants to an accuracy range of ±5% to ±1%. The tuning range, tuning accuracy and circuit non-idealities are analyzed theoretically. To verify the concept, an experimental chip was fabricated in JAZZ .18µm 1.8V CMOS technology. The tuning engine which occupies an area of .065mm2; consists of only an integrator, a comparator and a shift register. It can achieve a signal to noise and distortion ratio (SNDR) greater than 120dB over a ±40% tuning range. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

Circuitos integrados analógicos são essenciais em sistemas eletrônicos modernos, sendo responsáveis por tarefas como conversão analógica/digital e digital/analógica, comunicação por radiofrequência, filtragem, etc. O projeto deste tipo de circuito e sistema é de grande complexidade uma vez que deve atender a especificações de desempenho cada vez mais exigentes e ter um tempo de projeto reduzido a fim de não comprometer o tempo total dos projetos de sinal misto. Diversas ferramentas são propostas na literatura visando auxiliar o projetista a aumentar sua produtividade. Apesar disso, devido à forte interligação entre etapas, o fluxo de projeto de circuitos integrados analógicos ainda é, tradicionalmente, realizado utilizando-se apenas cálculos manuais e posterior ajuste fino através de softwares de simulação elétrica. Neste trabalho, são estudadas técnicas de síntese de circuitos analógicos utilizando métodos modernos de otimização em nível de circuito e sistema. Após este estudo, é proposto um novo algoritmo de Simulated Annealing/Simulated Quenching, incluindo um mecanismo para utilização do operador de crossover considerando informações de múltiplos objetivos. É realizada a hibridização entre o algoritmo desenvolvido e um algoritmo de Particle Swarm Optimization para criação de um segundo algoritmo capaz de realizar a busca pela fronteira de Pareto. As características dos algoritmos propostos foram elaboradas visando a síntese de circuitos integrados analógicos, no entanto, resultados indicam que eles também têm excelente desempenho em comparação com diversos algoritmos atuais do tipo sem derivada para determinados problemas matemáticos. A generalidade dos métodos modernos de otimização permite que variações da mesma técnica sejam utilizadas em nível de circuito (dimensionamento e polarização de componentes do circuito) e de sistema (tradução de especificações de sistema em especificações de blocos). Dessa forma, são propostas técnicas para a criação de uma ferramenta de síntese em nível de sistema e circuito utilizando métodos modernos de otimização. Uma interface através de arquivos texto de entrada foi desenvolvida para tornar a ferramenta versátil e poder ser utilizada para uma grande variedade de tipos de circuitos eletrônicos. Para validar o algoritmo e a ferramenta na síntese em nível de circuito, foram sintetizados circuitos em tecnologia 0,35 µm, 180 nm e 130 nm. Entre eles, foram sintetizados amplificadores do tipo Miller, amplificadores do tipo folded cascode complementar, amplificadores de baixo ruído operando em 2,45 GHz e fontes de referência. Comparações utilizando o teste não paramétrico de Mann-Whitney-Wilcoxon mostram que o algoritmo proposto tem melhor desempenho que os demais algoritmos comparados para os casos estudados. Comparações com projetos manuais e outras ferramentas confirmam a eficácia dos algoritmos e ferramenta. Para validação da ferramenta em nível de sistema, foram sintetizados filtros do tipo Gm-C. / Analog integrated circuits are very important in modern electronic systems, performing tasks such as analog to digital conversion, digital to analog conversion, radio frequency communication, filtering and others. The design of this type of circuit requires attending to several performance specifications as well as a time specification in order to avoid compromising the overall design time of mixed signal projects. Several tools are proposed in the literature in order to aid the designer, however the traditional design flow for analog integrated circuits is usually accomplished using only hand calculations and adjusts through the use of electrical simulators. In this work, techniques for analog design synthesis for circuit and system level are studied. An optimization algorithm is proposed based on Simulated Annealing/Simulated Quenching with a mechanism for using the crossover operator considering multiobjective information. An hybrid algorithm combining the proposed algorithm with Particle Swarm Optimization was created to properly explore the Pareto front The characteristics of the algorithms are made to enable the synthesis of analog integrated circuits, however, tests indicate they have excellent performance in comparison with many other derivative-free algorithms when applied to certain mathematical problems. The generality of modern optimization methods allow that variations of the same techniques can be used in circuit level (sizing and biasing of circuit components) and in system level (translation of system specifications to block specifications). Therefore, techniques for the creation of a circuit-level and system-level tool are developed. An interface using spice-like text files as inputs is developed to allow the designer to use the tool for a wide range of electronic circuits. In order to validate the proposed algorithms and circuit level tool, circuits were synthesized in 0.35 m, 180 nm and 130 nm. The synthesized circuits included Miller amplifiers, complementary folded cascode amplifiers, low noise amplifiers operating at 2.45 GHz and voltage reference circuits. Comparisons using the non-parametric Mann-Whitney-Wilcoxon test showed that the proposed algorithm has better performance than the compared algorithms for the studied cases. At the system level, syntheses of Gm-C filters were performed to validate the tool.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system.

This work considers alternative strategies to mainstream digital approaches to signal processing - namely analog and neuromorphic solutions, for increased computing efficiency. In the context of a speech recognizer application, we use low-power analog approaches for the signal conditioning and basic auditory feature extraction, while using a neuromorphic IC for building a dendritic classifier that can be used as a low-power word spotter. In doing so, this work also aspires to posit the significance of dendrites in neural computation.

Circuitos integrados analógicos são essenciais em sistemas eletrônicos modernos, sendo responsáveis por tarefas como conversão analógica/digital e digital/analógica, comunicação por radiofrequência, filtragem, etc. O projeto deste tipo de circuito e sistema é de grande complexidade uma vez que deve atender a especificações de desempenho cada vez mais exigentes e ter um tempo de projeto reduzido a fim de não comprometer o tempo total dos projetos de sinal misto. Diversas ferramentas são propostas na literatura visando auxiliar o projetista a aumentar sua produtividade. Apesar disso, devido à forte interligação entre etapas, o fluxo de projeto de circuitos integrados analógicos ainda é, tradicionalmente, realizado utilizando-se apenas cálculos manuais e posterior ajuste fino através de softwares de simulação elétrica. Neste trabalho, são estudadas técnicas de síntese de circuitos analógicos utilizando métodos modernos de otimização em nível de circuito e sistema. Após este estudo, é proposto um novo algoritmo de Simulated Annealing/Simulated Quenching, incluindo um mecanismo para utilização do operador de crossover considerando informações de múltiplos objetivos. É realizada a hibridização entre o algoritmo desenvolvido e um algoritmo de Particle Swarm Optimization para criação de um segundo algoritmo capaz de realizar a busca pela fronteira de Pareto. As características dos algoritmos propostos foram elaboradas visando a síntese de circuitos integrados analógicos, no entanto, resultados indicam que eles também têm excelente desempenho em comparação com diversos algoritmos atuais do tipo sem derivada para determinados problemas matemáticos. A generalidade dos métodos modernos de otimização permite que variações da mesma técnica sejam utilizadas em nível de circuito (dimensionamento e polarização de componentes do circuito) e de sistema (tradução de especificações de sistema em especificações de blocos). Dessa forma, são propostas técnicas para a criação de uma ferramenta de síntese em nível de sistema e circuito utilizando métodos modernos de otimização. Uma interface através de arquivos texto de entrada foi desenvolvida para tornar a ferramenta versátil e poder ser utilizada para uma grande variedade de tipos de circuitos eletrônicos. Para validar o algoritmo e a ferramenta na síntese em nível de circuito, foram sintetizados circuitos em tecnologia 0,35 µm, 180 nm e 130 nm. Entre eles, foram sintetizados amplificadores do tipo Miller, amplificadores do tipo folded cascode complementar, amplificadores de baixo ruído operando em 2,45 GHz e fontes de referência. Comparações utilizando o teste não paramétrico de Mann-Whitney-Wilcoxon mostram que o algoritmo proposto tem melhor desempenho que os demais algoritmos comparados para os casos estudados. Comparações com projetos manuais e outras ferramentas confirmam a eficácia dos algoritmos e ferramenta. Para validação da ferramenta em nível de sistema, foram sintetizados filtros do tipo Gm-C. / Analog integrated circuits are very important in modern electronic systems, performing tasks such as analog to digital conversion, digital to analog conversion, radio frequency communication, filtering and others. The design of this type of circuit requires attending to several performance specifications as well as a time specification in order to avoid compromising the overall design time of mixed signal projects. Several tools are proposed in the literature in order to aid the designer, however the traditional design flow for analog integrated circuits is usually accomplished using only hand calculations and adjusts through the use of electrical simulators. In this work, techniques for analog design synthesis for circuit and system level are studied. An optimization algorithm is proposed based on Simulated Annealing/Simulated Quenching with a mechanism for using the crossover operator considering multiobjective information. An hybrid algorithm combining the proposed algorithm with Particle Swarm Optimization was created to properly explore the Pareto front The characteristics of the algorithms are made to enable the synthesis of analog integrated circuits, however, tests indicate they have excellent performance in comparison with many other derivative-free algorithms when applied to certain mathematical problems. The generality of modern optimization methods allow that variations of the same techniques can be used in circuit level (sizing and biasing of circuit components) and in system level (translation of system specifications to block specifications). Therefore, techniques for the creation of a circuit-level and system-level tool are developed. An interface using spice-like text files as inputs is developed to allow the designer to use the tool for a wide range of electronic circuits. In order to validate the proposed algorithms and circuit level tool, circuits were synthesized in 0.35 m, 180 nm and 130 nm. The synthesized circuits included Miller amplifiers, complementary folded cascode amplifiers, low noise amplifiers operating at 2.45 GHz and voltage reference circuits. Comparisons using the non-parametric Mann-Whitney-Wilcoxon test showed that the proposed algorithm has better performance than the compared algorithms for the studied cases. At the system level, syntheses of Gm-C filters were performed to validate the tool.

Abstract Class A and class AB operational amplifiers are an essential part of a mixed- signal chip, where they are used as active filter sub-blocks, compensators, reference current generators and voltage buffers, to name just a few of many applications. For analog circuits such as operational amplifiers a mixed-signal chip is a very unfriendly operating environment, where the power supply is often corrupted by high current switching circuits. In addition, power supply voltages for analog blocks are shrinking, because of the deployment of new battery technologies and fine line length integrated circuit processes, which can reduce the amplifier dynamic range a problem requiring supply insensitive low voltage compatible amplifier topologies and other analog blocks. The aims of this thesis were to further develop the low voltage compatible class AB amplifier topologies published earlier by other authors, to improve their bandwidth efficiency by means of re-examining two- and three-stage amplifier compensation techniques and to find solutions for enhancing the high frequency power supply noise rejection performance of class A and class AB amplifiers without degrading their signal path stability. The class AB amplifier cores presented here improve the amplifier’s power supply noise insensitivity at high frequencies and increase bandwidth efficiency when compared to the commonly used two-stage Miller compensated amplifier, enabling the construction of better buffers and more power-efficient and reliable low voltage mixed signal chips.

Thesis (M.Sc.(Physics)) -- University of Limpopo, 2020 / Sperrylite (PtAs2), platarsite (PtAsS) and palladoarsenide (Pd2As) are platinum group minerals (PGMs) predominantly found in the Platreef Bushveld Complex in South Africa, which is one of the leading countries with highest percentages of platinum group minerals. In this study the density functional theory (DFT), embodied in the Vienna Ab-initio Simulation Package (VASP) code, was employed to investigate the structural, thermodynamically, elastic, mechanical, vibrational, electronic and surface properties of cubic PtAs2 and PtAsS, and monoclinic Pd2As mineral structures. The PtAsS was investigated from both virtual crystal approximations (VCA) solid solution within the Cambridge Serial Total Energy Package (CASTEP) code and the VASP cluster expansion (CE) approach. The cluster expansion phase stability was employed to generate new stable system of PtAsS model and from the cluster expansion binary ground state diagram we found a greater stability at 50/50 percentage (x = 0.5) of PtAsS where As and S atoms were equally distributed with formation of S-As dimer bond at the centre. The calculated lattice parameters were well reproduced and agreed with the available experimental data. The binary ground state diagram also showed that all structures have negative heats of formation (∆Hf), hence they were thermodynamically stable (miscible constituents). The calculated heats of formation predicted that PtAs2 was more stable than the PtAsS and the order of stability for cubic structures decreased as: PtAs2 > PtAsS (VCA) > PtAsS (CE).The elastic constants indicated mechanically stability for all structures and the phonon dispersion curves showed no soft modes for PtAs2, PtAsS (CE) and Pd2As, suggesting stability. Moreover, the elastic instability (negative Cij) was observed in the PtAsS (VCA) structure. We also observed that the Pd2As and PtAsS (CE) were ductile, while PtAs2 and PtAsS (VCA) were brittle. The calculated Young modulus indicated that PtAs2 was much stiffer compared to PtAsS models. This suggested that PtAs2 was mechanically stronger among all the cubic structures. The PtAs2 was a dominant covalently bonded compound whereas PtAsS and Pd2As were predicted as ionic bonded. The computed Bader charges for the bulk and surface PtAs2, PtAsS (CE) and Pd2As and Mulliken atomic charges for PtAsS (VCA) showed different behaviour. The Pt and Pd species showed negative charges, while As species showed a positive charge for PtAs2 and Pd2As. The PtAsS (CE) showed a negative charge for Pt and S species, while the PtAsS (VCA) showed a negative and a positive charges for Pt and As/S species. The calculated total density of states (TDOS) for the bulk PtAsS and Pd2As showed a metallic behaviour since there was no band gap at the Fermi energy (EF). The PtAs2 model was observed as a semiconductor with a band gap of 0.104 eV. From the DOS, PtAs2 was found the most stable since it had less contribution of DOS at the EF, while PtAsS and Pd2As structures showed least stability due to highest DOS at the EF. The understanding of the aspects of surface stability and preferred surface cleavage were investigated starting from surface terminations and then slab thickness for (100), (110) and (111) surfaces of all mineral structures. We found that (100) surface was the most stable, displaying the lowest positive surface energy for all the PtAs2, PtAsS and Pd2As minerals and was considered as the working surface. The order of surface stability decreased as: (100) > (111) > (110) for PtAs2 and PtAsS (VCA and CE) mineral systems and (100) > (110) > (111) for Pd2As system. Interestingly we found that the surface energies of the PtAsS (VCA) were smaller than for PtAsS (CE), which indicated that the VCA was more stable than the CE. The (100) surface was the most dominant on the surface morphology as expressed by the morphologies for all the mineral structures. Analysis of the DOS of the most stable (100) surface for PtAs2, PtAsS and Pd2As, we found that sperrylite and palladoarsenide showed a metallic behaviour since there was no band gap observed at the EF, while PtAsS surface structures showed a semiconductor behaviour due to presence of band gaps of 0.142 eV and 0.551 eV for PtAsS (CE) and PtAsS (VCA), respectively. The PtAsS (VCA) was found the most stable, while Pd2As was found the least stable. In addition, the intermediate stability was found for PtAsS (CE) and PtAs2 surface structures. These findings gave more insights on the stability of these minerals which may be applicable to their recovery / National Research Foundation (NRF) and Centre for High Performance Computing (CHPC)

Testing analog circuits is more difficult than digital circuits. The reasons for this difficulty include continuous time and amplitude signals, lack of well-accepted testing techniques and time and cost required for its realization. The traditional method for testing analog circuits involves measuring all the performance parameters and comparing the measured parameters with the limits of the data-sheet specifications. Because of the large number of data-sheet specifications, the test generation and application requires long test times and expensive test equipment. This thesis proposes an implicit functional testing technique for analog circuits that can be easily implemented in BIST circuitry. The proposed technique does not require measuring data-sheet performance parameters. To simplify the testing only time domain digital input is required. For each circuit under test (CUT) a cross-covariance signature is computed from the test input and CUT's output. The proposed method requires a training sample of the CUT to be binned to the data-sheet specifications. The binned CUT sample cross-covariance signatures are mapped with a supervised machine learning classifier. For each bin, the classifiers select unique sub-sets of the cross-covariance signature. The trained classifier is then used to bin newly manufactured copies of the CUT. The proposed technique is evaluated on synthetic data generated from the Monte Carlo simulation of the nominal circuit. Results show the machine learning classifier must be chosen to match the imbalanced bin populations common in analog circuit testing. For sample sizes of 700+ and training for individual bins, classifier test escape rates ranged from 1000 DPM to 10,000 DPM.