Bioelectronics effectively bridges the gap between the biochemical and the electrical domains, integrating aspects of biology, electronics, physics, and material science to foster innovative solutions and impact the trajectory of human health and environmental science, by translating biological responses into electrical signals for advanced analysis. Despite its transformative potential, current bioelectronic systems face limitations in terms of scalability, sensitivity, and ease of integration. This thesis claims that co-designing Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits with highly specific and sensitive genetically engineered biosensors is pivotal in bioelectronics evolution, offering high accuracy, reliability, miniaturization, and multiplexed sensing capabilities essential for addressing challenges in healthcare, environmental monitoring, sustainable manufacturing, and beyond. To support this claim, this dissertation highlights two key contributions: a low-power ingestible sensor for gastrointestinal tract monitoring and a hybrid platform technology combining droplet microfluidics and CMOS electronics for impedance spectroscopy and luminescence sensing for rapid screening and optimization of biosensors under different environmental conditions. The first contribution details an ingestible capsule that could transform healthcare diagnostics through a novel threshold-crossing-based detector and CMOS-integrated photodiodes. This innovation exemplifies how hybrid bioelectronic systems can significantly improve the precision and non-invasiveness of real-time health monitoring. Moving beyond the traditional scope of bioelectronics and the sole purpose of health monitoring, the second contribution extends its application by integrating droplet microfluidics with CMOS chips, facilitating high-throughput droplet screening to optimize biosensor performance for application deployment. To achieve this goal, this platform is equipped with a low-noise, high-resolution CMOS impedance spectroscopy chip and a high-resolution CMOS luminescence detector chip. In highlighting these contributions, the thesis reinforces the assertion that hybrid bioelectronic systems are key to addressing a wide range of societal challenges. Moreover, the integration of synthetic biology and microfluidics with CMOS technology, as demonstrated in this work, not only overcomes existing barriers, such as achieving miniaturization, high sensitivity, rapid data processing, and energy efficiency, but also paves the way for future innovations with extensive potential in personalized medicine and environmental sustainability. / 2026-01-17T00:00:00Z

Submitted by Sandro Camargo (sandro.camargo@unipampa.edu.br) on 2015-05-09T19:09:43Z No. of bitstreams: 1 117110018.pdf: 4311604 bytes, checksum: 0978b40aef931c296de315514d7d64ac (MD5) / Made available in DSpace on 2015-05-09T19:09:43Z (GMT). No. of bitstreams: 1 117110018.pdf: 4311604 bytes, checksum: 0978b40aef931c296de315514d7d64ac (MD5) Previous issue date: 2012-11-22 / A indústria de microeletrônica tem a sua evolução ditada pela necessidade cada vez maior de integração de circuitos como memórias e processadores, fazendo com que os dispositivos semicondutores sejam cada vez mais miniaturizados. Esta miniaturização implica processos de fabricação cada vez mais complexos, resultando em uma grande variabilidade de parâmetros. O projeto de circuitos analógicos torna-se cada vez mais complexo, pois em geral é altamente suscetível às variações de processo, o que afeta a sua produtividade. Uma das partes mais complexas deste projeto é o dimensionamento dos dispositivos que compõem o circuito, pois o espaço de projeto é altamente não-linear e nem sempre se conhece a localização do seu ponto ótimo. Neste contexto, este trabalho tem como objetivo o desenvolvimento de uma ferramenta para o dimensionamento automático de circuitos integrados analógicos, capaz de lidar com a variabilidade dos parâmetros e visando aumentar a produtividade do circuito gerado. Esta ferramenta baseia-se no dimensionamento do circuito como um problema de otimização baseado em simulação elétrica SPICE. O objetivo principal é receber as especificações requeridas de uma topologia de circuito e, através de técnicas de inteligência artificial, explorar o espaço de soluções em busca de soluções otimizadas que atendam às restrições impostas. Além disso, espera se obter soluções que atendam às especificações requeridas mesmo com variações no processo de fabricação. Para isso, são empregadas técnicas de design centering de modo a maximizar a produtividade do circuito. A ferramenta desenvolvida foi implementada de maneira modular, permitindo que a análise do dimensionamento do circuito possa ser realizada sob diferentes aspectos. Como resultado, este trabalho apresenta duas topologias de amplificadores operacionais automaticamente dimensionadas em tecnologia CMOS, tendo como objetivo a minimização da área de gate e da potência dissipada, além da maximização da produtividade. Os circuitos gerados apresentaram melhor desempenho em comparação com resultados descritos na literatura. / The microelectronics industry has the CMOS technology evolution dictated by the capability of integration of digital circuits such as memories and processors, causing the semiconductor devices miniaturization. The miniaturization leads to complex manufacturing processes with high parameters variation. Analog circuit designs are complex and highly susceptible to process variations, affecting the circuit yield. One of the most complex part of the analog design is the circuit sizing, since the possible solutions have a highly nonlinear design space and the optimal solution is not known. In this context, this work aims at developing a tool for the automatic sizing of analog integrated circuits that is able to deal with parameter variation in order to yield maximization. This tool is based on the circuit sizing as an optimization problem based on electrical SPICE simulations. The main objective is to receive the required specifications of a circuit topology and, by means of artificial intelligence techniques, to explore the design space for optimized solutions that meet the circuit constraints. Furthermore, it is expected to obtain solutions which meet the specifications required even with the presence of variations in the manufacturing process. For this purpose, design centering techniques are implemented for yield maximization. The tool is implemented with modular functions, enabling the sizing process on different configurations. As results, this work present the automatic design of two CMOS operational amplifiers topologies, with the goal to reduce the power dissipation and the gate area and to maximize the yield. The results present good performance when compared to similar designs found in literature.

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

This dissertation presents analog circuit analysis and design from a nonlinear dynamics perspective. An introduction to fundamental concepts of nonlinear dynamical systems theory is given. The procedure of nondimensionalization is used in order to derive the state space representation of circuits. Geometric tools are used to analyze nonlinear phenomena in circuits, and also to develop intuition about how to evoke certain desired behavior in the circuits. To predict and quantify non-ideal behavior, bifurcation analysis, stability analysis and perturbation methods are applied to the circuits. Experimental results from a reconfigurable analog integrated circuit chip are presented to illustrate the nonlinear dynamical systems theory concepts. Tools from nonlinear dynamical systems theory are used to develop a systematic method for designing a particular class of integrated circuit sinusoidal oscillators. This class of sinusoidal oscillators is power- and area-efficient, as it uses the inherent nonlinearity of circuit components to limit the oscillators' output signal amplitude. The novel design method that is presented is based on nonlinear systems analysis, which results in high-spectral purity oscillators. This design methodology is useful for applications that require integrated sinusoidal oscillators that have oscillation frequencies in the mid- to high- MHz range. A second circuit design example is presented, namely a bandpass filter for front end auditory processing. The bandpass filter mimics the nonlinear gain compression that the healthy cochlea performs on input sounds. The cochlea's gain compression is analyzed from a nonlinear dynamics perspective and the theoretical characteristics of the dynamical system that would yield such behavior are identified. The appropriate circuit for achieving the desired nonlinear characteristics are designed, and it is incorporated into a bandpass filter. The resulting nonlinear bandpass filter performs the gain compression as desired, while minimizing the amount of harmonic distortion. It is a practical component of an advanced auditory processor.

Τα αναλογικά φίλτρα συνεχούς χρόνου αποτελούν απαραίτητα μέρη ακόμη και στις πιο μοντέρνες ηλεκτρονικές συσκευές, οι οποίες λειτουργούν, κατά το μεγαλύτερο τμήμα τους ψηφιακά. Η εξήγηση είναι απλή, αν αναλογιστεί κανείς πρώτον, ότι, αποτελούν τις ενδιάμεσες βαθμίδες μεταξύ του φυσικού κόσμου και τις –κατά τα άλλα ψηφιακές– συσκευές και δεύτερον ότι, μπορούν να λειτουργήσουν σε υψηλές συχνότητες, όπου τα ψηφιακά κυκλώματα δεν μπορούν. Η προσπάθεια για όλο και πιο βελτιωμένα κυκλώματα, κάνει τους σχεδιαστές ηλεκτρονικών κυκλωμάτων να ψάχνουν για νέες μεθόδους σχεδίασης. Μία από αυτές είναι η σχεδίαση με χρήση τεχνικών τρόπου ρεύματος (current mode), χρήση της οποίας γίνεται στην παρούσα διδακτορική διατριβή. Είναι γνωστό ότι, έως και πριν από μερικά χρόνια, η σχεδίαση κυκλωμάτων γινόταν, σχεδόν αποκλειστικά, για λειτουργία σε τρόπο τάσης. Αυτό σημαίνει ότι, για τα κυκλώματα αυτά, οι ηλεκτρικές μεταβλητές εισόδου και εξόδου είναι τάσεις αφού, η είσοδος των χρησιμοποιούμενων ηλεκτρονικών βαθμίδων είναι υψηλής εμπέδησης ενώ η έξοδός τους χαμηλής. Τα κυκλώματα τρόπου τάσης σχεδιάζονται, ώστε, να λειτουργούν σε αυτές τις στάθμες εμπέδησης, παρά το γεγονός ότι, τα στοιχειώδη ηλεκτρονικά στοιχεία, τα τρανζίστορ, συμπεριφέρονται ως ελεγχόμενες πηγές ρεύματος. Αυτό ακριβώς το γεγονός εκμεταλλεύονται τα κυκλώματα τρόπου ρεύματος, τα οποία, λόγω του ότι εμφανίζουν χαμηλή εμπέδηση εισόδου και υψηλή εμπέδηση εξόδου, επεξεργάζονται ρεύματα απλοποιώντας ταυτόχρονα τον τρόπο σχεδίασης. Για να είναι πραγματικά εφικτή η σχεδίαση για τα κυκλώματα τρόπου ρεύματος είναι απαραίτητο ένα τουλάχιστον ενεργό δομικό στοιχείο. Στην παρούσα διατριβή ως δομικό στοιχείο μελετάται, καταρχήν, ο απλός ενισχυτής ρεύματος. Ο ενισχυτής αυτός αποτελεί τη βάση του διαφορικού ενισχυτή ρεύματος, που με τη σειρά του αποτελεί ένα νέο δομικό στοιχείο πολύ πιο ευέλικτο για ανάπτυξη νέων κυκλωμάτων αναλογικής επεξεργασίας σήματος. Προκύπτει ότι, ο διαφορικός ενισχυτής ρεύματος, ο οποίος λειτουργεί συνήθως, έχοντας ενίσχυση ρεύματος ίση ή λίγο μεγαλύτερη από τη μονάδα, μπορεί να δώσει κυκλώματα, που λειτουργούν σε υψηλότερες συχνότητες συγκριτικά με τα κυκλώματα τρόπου τάσης. Αρκετά κυκλώματα μπορούν να σχεδιαστούν με βάση, είτε τον απλό, είτε το διαφορικό ενισχυτή ρεύματος. Με τη βοήθειά των δύο αυτών στοιχείων αναπτύσσεται ένα πλήθος από βασικά κυκλώματα αναλογικής επεξεργασίας σήματος, όπως εξομοιωμένοι επαγωγοί, ολοκληρωτές, ταλαντωτές καθώς και ενεργά φίλτρα. Στη διατριβή αυτή, αναπτύσσεται, καταρχήν, η σχεδίαση διαφόρων βασικών αναλογικών δομικών βαθμίδων και ακολούθως, παρουσιάζονται οι τεχνικές για τη σχεδίαση ενεργών φίλτρων, ακολουθώντας δύο βασικές μεθόδους, όπως η μέθοδος διασύνδεσης βαθμίδων δεύτερης τάξης και η μέθοδος συναρτησιακής και τοπολογικής εξομοίωσης LC παθητικών κυκλωμάτων. Η μέθοδος της τοπολογικής εξομοίωσης κυκλωμάτων είναι αρκετά ελκυστική, λόγω των δυνατοτήτων, που προσφέρει. Είναι αρκετά εύκολη κατά το σχεδιασμό, τόσο τον ηλεκτρονικό όσο και τον φυσικό (layout), καθώς χρησιμοποιεί επαναλαμβανόμενες δομές. Δύο από τις τεχνικές, που ανήκουν στην κατηγορία της τοπολογικής εξομοίωσης κυκλωμάτων και αναπτύσσονται εδώ, είναι η σχεδίαση κυκλωμάτων με τεχνική τύπου "leapfrog" και η κυματική τεχνική. Με βάση τον διαφορικό ενισχυτή ρεύματος αναπτύσσεται ο τελεστικός ενισχυτής ρεύματος. Το στοιχείο αυτό είναι χρήσιμο σε εφαρμογές, όπου απαιτείται υψηλή ενίσχυση ρεύματος. Η ενίσχυση μπορεί να είναι μεταβαλλόμενη και εξαρτώμενη από μία τάση πόλωσης και αυτό κάνει τον τελεστικό ενισχυτή ρεύματος ένα αρκετά χρήσιμο στοιχείο στην ανάπτυξη εφαρμογών. Η ανάπτυξη ενός τελεστικού ενισχυτή ρεύματος παρουσιάζεται στο τέλος της διατριβής. Όλα τα κυκλώματα, που προτείνονται στην παρούσα διατριβή, είναι ολοκληρώσιμα σε οποιαδήποτε κοινή τεχνολογία ολοκλήρωσης. Ωστόσο, τα προτεινόμενα κυκλώματα σχεδιάζονται για CMOS τεχνολογία, επειδή είναι εξαιρετικά διαδεδομένη και κατάλληλη για τις περισσότερες εφαρμογές αναλογικής επεξεργασίας σήματος. Επιπλέον, τα CMOS κυκλώματα μπορούν σχετικά εύκολα να μετατραπούν σε διπολική ή και BiCMOS τεχνολογία, αφού τοπολογικά διατηρούν την ίδια περίπου δομή. / Continuous-time analog filters are essential parts even of the most modern electronic systems, which in their main part operate digitally. We can explain this by thinking, first, that analog circuits are usually used as necessary intermediate stages between the natural world signals and the electronic digital systems and second, that they are more suitable for operation at high frequencies compared to digital circuits. The designers of electronic circuits in their effort to improve circuits investigate for new design methods. Such a recent method is the so called "current-mode method". Current-mode circuits suitable, mainly for filtering applications, are studied in this thesis. It is known that until recently electronic circuits were considered as circuits operating in voltage-mode. This means that the electric variables for these circuits were taken mainly as voltages in spite of the fact that the elementary electronic devices, that is the transistors, behave as controlled current sources. On the contrary, current-mode circuits take advantage of the real nature of the transistors and thus process currents instead of voltages. This way, the circuit design procedure is significantly simplified, the derived current-mode circuits are much simpler in their structure and in addition, they show better performance at high frequencies. A structural active element is always necessary in every active filter either in the voltage or in the current-mode domain. In this thesis, a single input current amplifier is studied, as such structural active element. This amplifier is used as a subcircuit for obtaining the differential current amplifier, which, accordingly, is used as a new basic active device for the development of new analog signal processing circuits. It is found that the differential current amplifier, which usually operates having low current gain, is suitable for operation at high frequencies comparable to the fT of the transistors used in the amplifier. It is shown that various circuits of general purpose can be obtained, based on a single or a differential current amplifier. In addition, a number of new analog circuits suitable for signal processing are proposed in this thesis. Among them, there are lossy and lossless integrators, simulated inductors, and oscillators. However, emphasis is given to the development of integrated active filters of high order by following various design methods. As a result, the method of the topological simulation of passive LC filter prototypes appears to be more attractive for obtaining high order filters, due to the many possibilities that this method offers. All the proposed circuits in this thesis are suitable for integration in CMOS technology, which is more suitable for analog signal processing applications. Simulation and experimental results taken from implemented integrated circuits verify the accuracy of operation of the proposed circuits and their suitability for practical applications.

Submitted by Marlucy Farias Medeiros (marlucy.farias@unipampa.edu.br) on 2017-10-02T18:12:15Z No. of bitstreams: 1 Robson André Domanski - 2016.pdf: 5137261 bytes, checksum: 1e4aac0a601a8fb57b3a32e21268568a (MD5) / Approved for entry into archive by Marlucy Farias Medeiros (marlucy.farias@unipampa.edu.br) on 2017-10-04T17:34:54Z (GMT) No. of bitstreams: 1 Robson André Domanski - 2016.pdf: 5137261 bytes, checksum: 1e4aac0a601a8fb57b3a32e21268568a (MD5) / Made available in DSpace on 2017-10-04T17:34:54Z (GMT). No. of bitstreams: 1 Robson André Domanski - 2016.pdf: 5137261 bytes, checksum: 1e4aac0a601a8fb57b3a32e21268568a (MD5) Previous issue date: 2016-12-13 / O projeto de circuitos integrados analógicos, dentro da indústria da microeletrônica tem a sua evolução ditada pela grande necessidade da integração de circuitos mistos. Esta evolução faz com que os dispositivos semicondutores sejam cada vez mais miniaturizados, o que implica na complexidade cada vez maior no processo de fabricação, resultando em uma grande variabilidade de parâmetros. Esta complexidade no projeto está diretamente ligada ao dimensionamento dos dispositivos que compõem o circuito, já que o espaço de projeto é altamente não-linear. O dimensionamento de circuito analógico pode ser modelado como um problema de otimização e resolvido por heurísticas de otimização. A solução resultante é dependente da estratégia de modelagem e na estimativa de desempenho, o que é feito, em geral, por simulação elétrica. Neste contexto, foi desenvolvida a ferramenta UCAF. No entanto, a solução otimizada cai na fronteira do espaço de projeto, onde uma pequena variação nos parâmetros do dispositivo afeta o desempenho do circuito. Isso conduz à inclusão de simulação Monte Carlo no circuito de otimização, aumentando o esforço computacional. O objetivo principal deste trabalho é analisar dois métodos diferentes de amostragem, a fim de reduzir o número de rodadas Monte Carlo, e a inserção da heurística de otimização Particle Swarm Optimization, visando a minimização do tempo necessário para o dimensionamento do circuito. A amostragem por hipercubo latino, a qual requer um número menor de amostras para um nível de confiança razoável, é utilizado nas primeiras iterações do processo de otimização. Depois de um certo ponto, o método de amostragem é alterado para a amostragem aleatória tradicional. A heurística Particle Swarm Optimization foi implementada na ferramenta UCAF, devido ao seu baixo custo computacional. A metodologia é aplicada para o dimensionamento de um amplificador de transcondutância operacional OTA Miller e um amplificador Telescopic, mostrando vantagens em termos de tempo de processamento e desempenho do circuito. Pode-se demonstrar que a utilização de uma nova heurística, e diferentes métodos de amostragem para a simulação Monte Carlo no processo de otimização produz uma busca mais eficiente no espaço de projeto com um ganho em relação ao esforço computacional. / The analog integrated circuit design within the microelectronics industry has its evolution dictated by the great need for integration of mixed circuits. This trend makes the semiconductor devices are increasingly miniaturized, which implies the increasing complexity in the manufacturing process, resulting in a large variability op parameters. This complexity is directly linked to the design of devices that compose the circuit, since the design space is highly nonlinear. The design of analog circuit can be modeled as an optimization problem and solved by optimization heuristics. The resulting solution is dependent on modeling strategy and performance estimation, which is done generally by electrical simulation. In this context, the UCAF tool was developed. However, the optimized solution falls on the border of the design space where a small variation in device parameters affect circuit performance. This leads to the inclusion of Monte Carlo simulation on the circuit optimization, increasing the computational effort. The main objective of this study is to analyze two different methods of sampling, in order to reduce the number of Monte Carlo runs, and the inclusion of a new heuristic optimization, in order to minimize the time required for the design of the circuit. The Latin hypercube sampling, which requires a smaller number of samples for a reasonable confidence level is used in the first iteration of the optimization process. After a certain point, the sampling method is changed to the traditional random sampling. Heuristic Particle Swarm Optimization was implemented in UCAF tool, due to its low computational cost. The methodology is applied for the design of a Miller and a Telescopic operational transconductance amplifier, showing advantages in terms of processing time and circuit performance. We can demonstrate that the use of a new heuristic, and different methods of sampling for Monte Carlo simulation in the optimization process produces a more efficient search of the design space, and advantages in relation to computational effort.

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

Είναι γνωστό ότι τα κυκλώματα των τελεστικών ενισχυτών (Op-Amps) είναι από τις βασικότερες δομικές βαθμίδες στον χώρο της σχεδίασης αναλογικών ολοκληρωμένων κυκλωμάτων. Μια εναλλακτική δομή του τελεστικού ενισχυτή αποτελεί το κύκλωμα ενός Current Feedback Operational Amplifier (CFOA). Ένας CFOA είναι ουσιαστικά ένας μεταφορέας ρεύματος (Current Conveyor-CCII) σε σειρά με έναν ακολουθητή τάσης (Voltage Follower), και είναι ιδιαιτέρως χρήσιμος κατά την σχεδίαση κυκλωμάτων χαμηλής τάσης τροφοδοσίας. Στην εργασία αυτή μελετήθηκαν τέσσερις δομές CFOA, σχεδιασμένες για λειτουργία με χαμηλή τάση τροφοδοσίας, και χρησιμοποιήθηκαν για τον σχεδιασμό φίλτρων με τις μεθόδους Leapfrog, τοπολογικής εξομοίωσης και κυματική. Στο πρώτο κεφάλαιο αναφέρονται οι γενικές αρχές που ισχύουν στην σχεδίαση κυκλωμάτων για λειτουργία με χαμηλή τάση τροφοδοσίας καθώς και τις πιο συχνά χρησιμοποιούμενες τεχνικές σχεδίασης. Στο δεύτερο κεφάλαιο μελετώνται αναλυτικά οι τέσσερις δομές CFOA συγκρίνοντας τους βασικότερους παράγοντες απόδοσής τους. Τα κυκλώματα των CFOA που μελετώνται βασίζονται σε πρόσφατα δημοσιευμένες δομές Current Conveyor (CCII). Στο τρίτο κεφάλαιο αναλύεται η μέθοδος σχεδίασης φίλτρων Leapfrog, και χρησιμοποιείται για την σχεδίαση ενός Butterworth φίλτρου 3ης τάξης. Ως δομική βαθμίδα για την σχεδίαση αυτού του φίλτρου χρησιμοποείται ο CFOA [2]. Το τρίτο κεφάλαιο ολοκληρώνεται με την παρουσίαση των βασικότερων παραγώντων απόδοσης. Στο τέταρτο κεφάλαιο παρουσιάζεται η τοπολογική μέθοδος σχεδίασης φίλτρων, στην οποία γίνεται τοπολογική αντικατάσταση πηνίου, σε παθητικό φίλτρο, από ισοδύναμο κύκλωμα με ενεργά στοιχεία. Και στην περίπτωση αυτή η δομική μονάδα σχεδιασμού είναι ο CFOA [2]. Στο πέμπτο κεφάλαιο παρουσιάζεται η σχεδίαση ενός Butterworth φίλτρου 3ης τάξης με την κυματική μέθοδο. Η σχεδίαση πραγματοποιήθηκε χρησιμοποιώντας ως δομική βαθμίδα τον CFOA [1]. Στο έκτο κεφάλαιο παρουσιάζεται η φυσική σχεδίαση (layout) του Butterworth φίλτρου 3ης τάξης που σχεδιάστηκε με την leapfrog μέθοδο στο τρίτο κεφάλαιο. Η φυσική σχεδίαση πραγματοποιήθηκε με την χρήση του λογισμικού Cadence και του περιβάλλοντος Virtuoso που περιλαμβάνει για την φυσική σχεδίαση αναλογικών ηλεκτρονικών κυκλωμάτων . Τέλος στο έβδομο κεφάλαιο γίνεται σύγκριση των αποτελεσμάτων εξομοίωσης των δομών CFOA’s αλλά και των αποτελεσμάτων εξομοίωσης των φίλτρων που σχεδιάστηκαν στα παραπάνω κεφάλαια . Επίσης παρουσιάζονται κάποιες προτάσεις για μελλοντική και περαιτέρω έρευνα. / Operational amplifier is one of most important analog building block. An alternative structure for operational amplifier is a Current Feedback Operational Amplifier (CFOA). A CFOA is essentially consists of a current conveyor (CCII) connecting with a Voltage Follower (VF). The usage of CFOA for the low-voltage analog IC design is quite useful. In this work four different CFOA structures, designed for low-voltage operation, were considered. Also the aforementioned CFOAs were used to build a butterworth filter with Leapfrog method, topological simulation method and wave method. In first chapter the basic design rules and the most common design techniques for low-voltage IC design is presented. In chapter 2 the four structures of CFOAs circuits were considered, under the light of comparison of most critical factors of operation. The CFOAs circuits were based in most resent published topologies of Current Conveyor (CCII). In chapter 3 the Leapfrog method for filters design was discussed. Also a 3rd order butterworth filter is designed based on this method. The CFOA of ref [2] is the main building lock to construct this filter. In chapter 4 another method for filter design is presented named topological simulation method. According to this method passive elements such as inductors and capacitors are replaced by active elements. The main building block is also CFOA of ref [2]. In Chapter 5 a 3rd order butterworth filter based on wave method is designed. In this case the main building block was the CFOA circuit of ref [1]. Chapter 6 presents the layout of the 3rd order butterworth filter which designed at chapter 3 with leapfrog method. The layout design was implemented using Virtuoso environment of Cadence design framework II platform. Chapter 7 conclude this work presenting the simulated comparison results for all four CFOAs circuits and the 3rd order butterworth filters that were designed with the three different methods. Some thoughts for further research in the this subject are also presented.

Οι συνεχώς αυξανόμενες ανάγκες της σημερινής αγοράς για φορητές ηλεκτρονικές συσκευές και τηλεπικοινωνιακά συστήματα χαμηλής τάσης τροφοδοσίας και χαμηλής κατανάλωσης ισχύος, καθιστά απαραίτητη τη σχεδίαση ενεργών βαθμίδων οι οποίες θα είναι ικανές να λειτουργήσουν σε ένα περιβάλλον όπου μία απλή τάση τροφοδοσίας μικρότερη ή ίση με 1.5V είναι διαθέσιμη. Έτσι, στην εργασία αυτή θα γίνει μια μελέτη διαφορετικών ενεργών βαθμίδων που δύνανται να λειτουργήσουν στο περιβάλλον αυτό, συγκρίνοντας τις δυνατότητες τους. Η μελέτη αυτή αφορά στις ενεργές βαθμίδες CCII και CFOA, καθώς και σε παραλλαγές τους που αφορούν στη λειτουργία των βαθμίδων αυτών με διαφορική τάση εισόδου (DVCCII και DVCFOA).Απώτερος σκοπός της σύγκρισης των βαθμίδων αυτών, αποτελεί η εφαρμογή τους στη σχεδίαση και υλοποίηση μιγαδικών φίλτρων. Έτσι, έπειτα από μία πλήρη περιγραφή των μιγαδικών φίλτρων ώστε να κατανοηθεί η λειτουργία τους, αλλά και των προβλημάτων που εισάγουν την ανάγκη χρήσης τέτοιων φίλτρων, θα μελετηθεί η χρησιμότητα καθεμιάς από τις παραπάνω ενεργές βαθμίδες στη σχεδίαση μιγαδικών φίλτρων ανώτερης τάξης, τα οποία πληρούν τις προδιαγραφές της εκάστοτε τεχνολογίας. Συγκεκριμένα θα γίνει η σχεδίαση και υλοποίηση ενός μιγαδικού φίλτρου 12ης τάξης ικανού να λειτουργεί (κατ’ επιλογή) τόσο για ένα κανάλι μετάδοσης μέσω του πρωτοκόλλου Bluetooth, όσο και για ένα κανάλι μετάδοσης μέσω του πρωτοκόλλου ZigBee.Τελικό βήμα της εργασίας, αποτελεί η φυσική σχεδίαση του κυκλώματος που θα προκύψει, ώστε να επαληθευτεί η ορθή λειτουργία του σε ένα περισσότερο ρεαλιστικό περιβάλλον. / The ever-increasing needs of today's market for portable electronic devices and telecommunication systems of low voltage and low power consumption, necessitates the design of active building blocks that are likely to operate in an environment where a single supply voltage less than or equal to 1.5V is available. Thus, this work will be a study of different active building blocks that may operate in this environment, comparing their abilities. The study refers to active building blocks CCII and CFOA, as well as variations related to their operation involving differential input voltage (DVCCII and DVCFOA). The ultimate goal of comparing these blocks is their application in the design and implementation of complex filters. Thus, after a full description of complex filters to understand their functioning and the problems that introduce the need to use such filters, the usefulness of each of these blocks will be studied in the design of higher-order complex filters, which meet the specifications of each technology. In particular a 12th order complex filter able to function (optional) for both a transmission channel over Bluetooth Protocol, and a transmission channel over ZigBee Protocol, will be designed and implemented. Final step of the work is the physical layout of the circuit, so as to verify the proper functioning in a more realistic environment.

L'environnement spatial constitue une contrainte radiative susceptible d'altérer le bon fonctionnement des dispositifs électroniques embarqués à bord des engins spatiaux, engendrant ainsi des défaillances. Dans le cadre de ces travaux, deux types de dysfonctionnements sont répertoriés : les effets cumulatifs dus à une accumulation continue d'énergie déposée tout au long d'une mission et les effets transitoires dus au passage d'une particule unique dans une zone sensible d'un composant ou à un dépôt d'énergie en un temps très court dans le cadre spécifique d'une explosion nucléaire exoatmosphérique. Lors des procédures de qualification des composants électroniques, ces deux effets sont traités séparément et ce, malgré une probabilité non négligeable qu'ils se produisent simultanément en vol. Ces travaux sont dédiés à l'étude de la synergie entre effets cumulatifs et effets transitoires sur différentes technologies bipolaires intégrées. Les résultats obtenus permettent de fournir des éléments de réponse sur l'éventualité d'une évolution des normes de test pour prendre en compte la menace que pourrait représenter ce phénomène. Ces travaux s'attachent également à étendre une méthodologie de simulation, basée sur une analyse circuit approfondie, dans l'optique de reproduire les perturbations transitoires « pire-cas » sur un amplificateur opérationnel à trois étages de plusieurs fabricants, survenues lors des tests sous faisceau laser, ions lourds et flash X. L'influence des effets cumulatifs sur la sensibilité des perturbations transitoires est prise en compte en faisant varier les paramètres internes du modèle en fonction de la dégradation de certains paramètres électriques issue des essais radiatifs des équipementiers. / The space environment is a radiative concern that affects on board electronic systems, leading to failures. It is possible to distinguish two types of effects: the cumulative effects due to continuous deposition of energy throughout the space mission and the transient effects due to the single energetic particle crossing a sensitive area of the component or deposition of energy in a very short time in the specific context of an exo-atmospheric nuclear explosion. During qualification procedures for space mission, these effects are studied separately. However, the probability that they occur simultaneously in flight is significant. As a consequence, this work is about the study of the synergy between both cumulative and transient effects on various integrated bipolar technologies. The present results are used to provide some answers about potential changes of test methods. This work also evaluates the predictive capability of the previously developed model to reproduce accurately both the fast and the long lasting components of transients in circuitry and so to model transients' effects. This simulation methodology is extended to an operational amplifier from different manufacturers and for three different synergistic effects. The comparison between transients obtained experimentally during heavy ions, pulse laser and flash X experiments and the predicted transients validates the investigated methodology. The cumulative effects are taken into account by injecting the internal electrical parameters variations using irradiation exposure.