Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

RF switches are an essential building block in numerous applications, including tactical radar systems, satellite communications, global positioning systems (GPS), automotive radars, wireless communications, radio astronomy, radar transceivers, and various instrumentation systems. For many of these applications the circuits have to operate reliably under extreme operating conditions, including conditions outside the domain of commercial military specifications. The objective of this thesis is to present the design procedure, simulation, and measurement results for Radio Frequency (RF) switches in 130 nm Silicon Germanium (SiGe) BiCMOS process technology. The novelty of this work lies in the proposed new topology of an ultrahigh-isolation single-pole, single-throw (SPST) and a single pole, four-throw (SP4T) nMOS based switch for multiband microwave radar systems. The analysis of cryogenic temperature effects on these circuits and devices are discussed in this work. The results shows that several key-figures-of-merits of a switch, like insertion loss, isolation, and power handling capability (P1dB) improve at cryogenic temperatures. These results are important for several applications, including space-based extreme environment application where FET based circuits would need to operate reliably across a wide-range of temperature.