Thesis (M.S. in Engineering Science (Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): David C. Jenn, Roberto Cristi. Includes bibliographical references (p. 75-76). Also available online.

Thesis (M. Eng. Sc.)--University of Queensland, 2002. / Includes bibliographical references.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 219-224). Also available online.

The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One way to address the computational and communication challenges of such demanding applications is to incorporate the use of non-conventional hardware accelerators such as FPGAs into existing systems. By providing a mix of FPGAs and conventional CPUs as computing resources in a heterogeneous cluster, a distributed computing environment can be achieved to address the need of both compute-intensive and data-intensive applications. However, utilizing heterogeneous clusters requires application developers’ comprehensive knowledge on both hardware and software. In order to assist programmers to take advantage of the synergy between hardware and software easily, an easy-to-use framework for virtualizing the underlying FPGA computing resources of the heterogeneous cluster is motivated. In this work, a heterogeneous cluster consisting of both FPGAs and CPUs was built and a framework for managing multiple FPGAs across the cluster was designed. The major contribution of the framework is to provide an abstraction layer between the application developer and the underlying FPGA computing resources, so as to improve the overall design productivity. An inter-FPGA communication system was implemented such that gateware executing on FPGAs can communicate with each other autonomously to the CPU. Furthermore, to demonstrate a real-life application on the heterogeneous cluster, a generic k-means clustering application was implemented, using the MapReduce programming model. The implementation of the k-means application on multiple FPGAs was compared with a software-only version that was run on a Hadoop multi-core computer cluster. The performance results show that the FPGA version outperforms the Hadoop version across various parameters. An in-depth study on the communication bottleneck presented in the system was also carried out. A number of experiments were specifically designed to benchmark the performance of each I/O channel. The study shows that the major source of I/O bottleneck lies at the communication between the host system and the FPGA. This gives insight into programming considerations of potential applications on the cluster as well as improvement to the framework. Moreover, the benefit of multiple FPGAs was investigated through a series of experiments. Compared with putting all mappers on a single FPGA, it was found that distributing the same amount of mappers across more FPGAs can provide a tradeoff between FPGA resources and I/O performance. / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

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published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

Στο πλαίσιο αυτής της εργασίας μελετήθηκαν οι διατάξεις επεξεργαστών και πιο συγκεκριμένα οι συστολικές διατάξεις επεξεργαστών. Επίσης αναπτύχθηκε CAD εργαλείο για την αυτόματη VLSI σχεδίαση συστολικών διατάξεων επεξεργαστών για αλγόριθμους επεξεργασίας σήματος. / In this book were studied the processor arrays and more concretely the systolic processor arrays. Also was developed CAD tool for the automatic VLSI designing of systolic processor arrays on signal processing algorithms.

In this work, we study the enhanced endwall heat transfer for flow past non conducting pin fin arrays. The aim is to resolve the controversy over the heat transfer that is taking place from the endwall and the pin surface.Various parameters were studied and results were obtained. Our results are found to be consistent with some of the results that have been previously published. The results were surprisingly found to be dependent on the height of the pin fin.

No description available.