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Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced by scan cells, due to the area cost and the timing-critical nature of many of the paths into and out of memories. Thus, bits in a memory array can be considered non-scan storage elements. Test methods such as memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these tests aren’t sufficient to test the paths through the memory arrays. During structural (scan) test generation, memory arrays are treated as “black boxes” or memory arrays are bypassed to a known value. Black boxes decrease coverage loss while bypassing increases chip area and delay. Path delay test through memory arrays is proposed using pseudo functional test (PFT) with K Longest Paths Per Gate (KLPG). In this technique, any longest path that is captured into a non-scan cell (including a memory cell) is propagated to a scan cell. The propagation of the captured value from non-scan cell to scan cell occurs during low-speed clock cycles. In this work, we assume that only one extra coda cycle is sufficient to propagate the captured value to a scan cell. This is true if the output of the memory feeds combinational logic that in turn feeds scan cells. When we want to launch a transition from a memory output, different values are written into different address locations and the address is toggled between the locations. The ATPG writes the different values into the memory cells during the preamble cycles. In the case of launching a transition out of a non-scan cell, the cell must be written with an initial value during the preamble cycles, and the next value set on the non-scan cell input. Thus, it is possible to capture and launch transitions into and from memory and non-scan cells and thus test the path delay of the longest paths into and out of memory and non-scan cells.

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Microelectrodes have been found to be a valuable tool in a variety of analytical studies. Their advantages over macro-sized electrodes are well known, including their enhanced mass transport properties (due to their ubiquitous hemispherical diffusion) which lead to steady state responses without external convection. They also exhibit high signal-to-noise ratios (greater sensitivities), furthering their analytical application. Microelectrode arrays are analytical devices with multiple electrodes. There are suitable for practical sensing with all the benefits of microelectrodes but with greater currents, leading to greater ease of measurement. To produce a reliable electroanalytical device the microelectrode response must be reproducible, a fundamental property based on the quality control of their production. Square microelectrode and array fabrication techniques have been developed for this purpose. This research discusses the fabrication and development of closely spaced arrays of square microelectrodes. Simulated and measured responses are compared and used to characterize electrode and array responses by cyclic voltammetry, electrical impedance spectroscopy and current-time transients. Measurements on variably spaced arrays allow insight into overlap of hemispherical diffusion from individual electrodes and the subsequent effect including peak current output on the array device. By studying these devices key insights into the mass transport properties of single square microelectrodes and microelectrode arrays were gained. This study also prepares and develops microelectrodes from materials appropriate for use in the extreme environments of molten salts and concentrated nitric acid solutions. These robust electrodes were developed for use in hydro- and pyro-chemical techniques for nuclear fuel reprocessing. These results demonstrate the practical uses for microelectrode systems across a wide range of chemical systems and in extreme conditions.

In Multiple-Input Multiple-Output (MIMO) broadcast channels, the multi-antenna basestation transmits information to multiple non-cooperative mobile users simultaneously. Among various transmission schemes, zero-forcing beamforming (ZFBF) and random unitary beamforming (RUB) are of particular interest due to their low implementation complexity and ability to explore the multiplexing gain provided by multiple transmit antennas. To investigate the effects of multiuser diversity on sum-rate performance, previous studies of beamforming schemes in multiuser MIMO systems usually employ asymptotical analysis. In this work, while assuming channel gain follows Rayleigh flat fading, we study the sum-rate performance of ZFBF and RUB through exact mathematic analysis. For this purpose, we derive the statistics of selected users's effective channel gain, which enable us to calculate the sum rate accurately and efficiently. With derived sum-rate expressions, we evaluate and compare the sum-rate performance of MIMO broadcast channels with RUB and dual-transmit-antenna ZFBF. In addition, we apply this analytical method to study strategies that mitigate multiuser interference for RUB-based multiuser MIMO systems. The strategies we consider in the thesis include • Reducing the number of served users at a time. We present a new user scheduling scheme, which imposes a threshold On user's SINR for feedback load reduction and only activates those beams that are requested by feedback users. • Exploiting receive diversity. When receivers use more than one antennas, we evaluate the sum-rate performance gain offered by selection combining (SC) and optimum combining (OC) schemes, respectively. In addition to beamforming techniques, we study the symbol error rate (SER) performance of MIMO broadcast channels with vector perturbation (VP) precoding and quantized channel feedback. Based. on the established equivalent relations in terms of minimum mean square error (MMSE) and SER between quantized and perfect channel feedback cases, we investigate the tradeoff between feedback load and achievable diversity gain. / Graduate

A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT). A significant part of the FPGA market is occupied by devices based on more than one type of lookup tables. Examples of these heterogeneous LUT-based FPGAs are the Xilinx 4000 series devices. The technology mapping for this class of FPGAs has hardly been considered. This thesis covers work on the synthesis for heterogeneous LUT-based FPGAs. The proposed scheme uses the typical steps of graph covering, decomposition, node elimination and Boolean graph simplification. The covering step is based on the concept of flow networks and cut-computation. A theory is devised that reduces the flow network sizes so that a dynamic programming approach can be used to compute the feasible cuts in the network. An iterative selection algorithm can then be used to compute the set cover of the network. For the decomposition, the conventional bin-packing (cube-packing) algorithm has been extended so that it produces two types of bins. It has also been enhanced to explore several packing possibilities and include cube division and cascading of nodes. The classical functional decomposition method is extended to heterogeneous graphs. In particular, variable partitioning is coupled with other decomposition methods and exploits the structure of the functions. Partial collapsing and re-decomposition are used to re-synthesise the graphs. A strategy for eliminating nodes within a heterogeneous graph is developed. A simplification strategy is also derived from logic optimisation techniques. Comparisons of the mapping results on Xilinx devices show an improvement of over 11% over existing mapping tools for the same devices.

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