This work explores the interaction of electromagnetic radiation with periodic metal-dielectric composite materials. In particular, the majority of the studies explore the role of evanescent diffraction in the regime where the wavelength of the incident radiation is of the order of the period of the array just below the onset of diffraction. The underlying aim of the thesis is to build on the current knowledge and gain deeper understanding into the causal mechanism of the electromagnetic response of these periodic materials. Developments in metamaterial research have led to a resurgance of interest in the use of periodic metallic surface to control the transmission of electromagnetic radiation. The response of these surfaces can be `tuned' to provide the required response simply by altering the geometric parameters of the material. Numerical modelling techniques are often used to predict the response of such structures. However, the aim of this work is to gain a deeper understanding of the reasons for the response and therefore an analytical modal matching method has been used. The modal matching method provides the opportunity to extract greater understanding of the resonant phenomena by linking them to specific mathematical terms in the analytical formulation. The modal matching technique is initially used to study the response from a single layer bigrating comprising a square array of square holes in a PEC sheet and its complementary system of a square array of square PEC patches. The importance of evanescent diffraction in both resonant phenomena and tunneling responses is discussed and it is shown that complete transmission (reflection) is supported by these structures even for very high (low) metal occupancy. This technique is extended and adapted to describe a variety of structures in chapters 5 and 6, exploring how resonant excitation of surface waves via evanescent diffraction leads to highly interesting electromagnetic responses. In chapter 7, alternating multilayer stacks of two different subwavelength meshes provide an observable one-dimensional topological mode in a physical system for particular mesh configurations.

Les Maladies Inflammatoires Chroniques de l’Intestin (MICI) regroupent la maladie de Crohn (MC) et la Rectocolite Hémorragique (RCH), deux maladies qui se caractérisent par l’inflammation de la paroi d’une partie du tube digestif, source de lésions destructrices (ulcérations). Ces pathologies complexes sont influencées par de multiples facteurs génétiques et environnementaux. D’une part, de nombreux gènes de susceptibilité pour ces maladies ont été identifiés, mais ils ne permettent d’expliquer qu’une fraction mineure du développement des MICI. D’autre part, certaines études montrent qu’un dysfonctionnement du processus de prise en charge des xénobiotiques dans la muqueuse digestive peut jouer un rôle dans l’initiation et/ou la progression des MICI. Notre travail a consisté, dans un premier temps, en l’étude du profil d’expression de gènes codant pour des protéines impliquées dans le métabolisme et le transport des xénobiotiques. Une stratégie de RT-PCR quantitative en temps réel, permettant l’analyse simultanée de l’expression de 377 gènes, a été utilisée. Cette analyse a été réalisée sur des échantillons de muqueuse intestinale de sujets témoins et de patients atteints de MC, ainsi que sur cinq lignées de cellules épithéliales intestinales.Cette étude a permis d’identifier les systèmes de prise en charge des xénobiotiques présents dans la muqueuse intestinale saine. Des profils d’expression différents ont été mis en évidence entre les tissus intestinaux sains et inflammatoires, mais également entre les tissus intestinaux et les lignées cellulaires intestinales, ce qui suggère des différences majeures dans les processus de prise en charge cellulaire des xénobiotiques, et, par conséquent des différences de susceptibilité à l’effet des composés toxiques exogènes. Dans un second temps, la petite protéine G, Rac1, a été étudiée. Cette protéine est impliquée dans la réparation des ulcérations de l’épithélium intestinal et a récemment été identifiée comme la cible des métabolites actifs des médicaments thiopuriniques, largement prescrits dans le traitement des MICI. La nature et l’étendue de la variabilité de la séquence nucléotidique du gène Rac1 a été évaluée, chez des volontaires sains et des patients atteints de MICI, à l’aide d’une stratégie basée sur le couplage de l’analyse du polymorphisme de conformation de fragments d’ADN simple brin générés par réaction de polymérisation en chaine (PCR-SSCP) et du séquençage. Des études in silico et in vitro des conséquences fonctionnelles des polymorphismes d’intérêts ont ensuite été effectuées dans des lignées cellulaires intestinales (HT29 et Caco-2) et lymphocytaires (Jurkat). Cela nous a conduits à mieux caractériser le promoteur de Rac1 par une analyse de délétion séquentielle et par des techniques de ChIP et d’EMSA.Cette étude nous a permis de démontrer pour la première fois l’existence de polymorphismes génétiques fonctionnels de Rac1 et d’identifier son promoteur minimal, ainsi que des facteurs de transcription à l’origine de la régulation de cette protéine. / Crohn’s disease (CD) and Ulcerative colitis (UC) are chronic inflammatory bowel diseases (IBD) of the gastrointestinal tract. These are multifactorial polygenic diseases with probable genetic heterogeneity. An emerging concept suggesting that dysfunction(s) of the processing of xenobiotics in the intestinal mucosa may be an important event in the initiation and progression of IBD has been discussed. Firstly, in this study, a precise and reliable characterization of the global expression profile of genes which code enzymes, transporters and nuclear factors involved in the processing of xenobiotics has been performed in intestinal epithelium of controls or patients with IBD, and in 5 intestinal cell lines. A quantitative real-time RT-PCR analysis using TaqMan Low Density Arrays (TLDA) was performed to simultaneously measure the expression of 377 genes.This work has identified genes encoding proteins that are involved in the metabolism and the disposition of xenobiotics in the healthy intestinal mucosa. Different genes expression profile between healthy and inflammatory intestinal tissues and between healthy intestinal tissues and intestinal cell lines were found. These tissues will consequently display distinctive susceptibility toward environmental chemicals and their toxic effects.Secondly, the small G protein, Rac1, which regulates cutaneous and mucosal intestinal wound healing and is identified as a target of active metabolites of thiopurine drugs, used in the treatment of IBD, has been studied. We searched for sequence variations by analysing the nucleotide sequence of the promoter and the coding sequence of Rac1 in genomic DNA from healthy volunteers and patients with IBD, using a PCR-single strand conformation polymorphism (SSCP) strategy and sequencing. The functional consequences of variations, that have been identified, were then analysed in silico and in vitro, in human intestinal cell lines (HT29 and Caco-2) and leukemia T-lymphocyte cell line (Jurkat). Via various deletion constructs, a putative regulatory region was identified and characterized further by chromatin immunoprecipitation and electrophoretic mobility shift assays.This work provides the first evidence that a functional genetic polymorphism of Rac1 activity exists. Furthermore, this study characterizes the proximal promoter of Rac1 gene and demonstrates the presence of consensus binding sites for numerous transcription factors, which could influence gene expression.

Approved for public release; distribution is unlimited / The harsh radiation environment of space, the propensity for SEUs to perturb the operations of a silicon based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low cost, rapidly developed system solutions. Consequently, a reconfigurable Triple Modular Redundant (TMR) System-on-a-Chip (SOC) utilizing Field Programmable Gate Arrays (FPGAs) provides a viable solution for space based systems. The Configurable Fault Tolerant Processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, the reliability of instantiated TMR soft-core microprocessors, as well as the ability to reconfigure the system to support any onboard processor function. The CFTP maximizes the use of Commercial Off-The-Shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a Total Ionizing Dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, will enable on-orbit upgrades, reconfigurations, and modifications to the architecture in order to support dynamic mission requirements. The CFTP payload consists of a Printed Circuit Board (PCB) of 5.3 inches x 7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration will be an instantiation of a TMR processor, with included Error Detection and Correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and Flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a Space Test Program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites. / Major, United States Marine Corps

隨著半導體生產工藝的特徵尺寸日益縮小，工藝變化引起的良率損失亦日益顯著。在現場可編程門陣列平臺，一些優化設計方法根據芯片的特定的工藝變化特徵來優化設計以提高時序良率。然而，目前缺乏一種實際的工藝變化特徵提取方法以支持上述優化設計方法。為了滿足這一需求，在文論文的第一部份，我們提出利用環形振盪器來提取商用現場可編程門陣列芯片的工藝變化特徵。該方法可以提取到邏輯單元級別的時序特徵，并進而推測出互聯電路的時序特徵。為了證明該方法的有效性我們在現場可編程門陣列芯片上任意放置兩個結構完全相同的環形振盪器于不同的位置。我們分別通過直接測量和通過分析特徵提取的數據得到兩振盪器的時序差異。對比結果顯示通過分析特徵提取數據，推算結果和實際測量結果僅平均相差10% 以內。我們在Xilinx 公司的Spartan-3e 芯片上實現了該方法，別且在其他Xilinx 的芯片上同樣適用。 / 在本論文的第二部份，我們提出一種利用現場可編程門陣列架構對稱性的方法來系統化的改變設計道路。通過對一個初始設計電路的旋轉和翻轉，我們可以得到八種時序性能相同的候選設計。在隨機工藝變化的存在下，八種候選設計的任何一個都有同樣的可能性被選為針對某一特定芯片的最優設計。如果大批芯片的單一個體都可以確定最優設計，整體性能將大幅度改善。另外，我們提出交換關鍵路徑上的相鄰邏輯單元來進一步提高時序性能通過對二十個測試電路的仿真實驗，我們發現統計時序性能得到了大幅度改善。相比于其他改善時序性能的方法，該方法從設計時間的角度來看更有效率。 / 雖然工藝變換常被認為一種有害的寄生效應，但是它提供了一些應用前景。物理費克隆方程的提出啟發研究人員把芯片的工藝變化的唯一性轉化為芯片的數字身份。在本論文的第三部份，我們提出利用環形振盪器陣列來測量工藝變化，并通過比較振盪器的相對速度來計算芯片數字身份。然而，芯片身份的穩定性是一個普遍的問題，尤其是在考慮到工作環境(如溫度、這墨)改變的情況下。為了解決這一間包我們提出結合使用可配置的環形振盪器以及重新初始化的方法來提高穩定性。改方法同樣在Xilinx 的Spartan-3e 芯片上實現。實驗結果表明該方法大幅度提高了在工作環境變化下芯片身份的穩定性。 / As semiconductor manufacturing continues towards reduced feature size, yield loss induced by process variation becomes increasingly significant. On the platform of field programmable field array (FPGA), several works proposed to improve timing yield by optimizing design implementation based on chip-specific variation distribution, which are generally defined as variation aware design (VAD) methods. However, there is a lack of practical variation characterization method to facilitate the invented VAD methods. To fulfill this demand, in the first part of this thesis, we proposed to characterize delay variation by measuring the loop delay of ring oscillator (RO) on commercial FPGAs. By comparing the difference of loop delays for ROs with slightly different structures, the logic element (LE) delay can be explicitly characterized. The delays of interconnect circuits can be further derived with existing LE delay information and additional measurements. To evaluate the effectiveness of the proposed variation characterization, two ROs with identical structure are arbitrarily placed at different locations on an FPGA chip. The difference of the loop delays between two ROs can be both directly measured and estimated by characterization results. Taking measurement results as references, the error rate of estimation by characterization results is less than 10% on average. The proposed characterization method is implemented on Xilinx Spartan-3e FPGA chips. Without loss of generality, the proposed method can be also adopted on other Xilinx FPGA devices. / In the second part of this thesis, we proposed to systematically manipulates FPGA post-layout circuits by using FPGA architectural symmetry. Eight timing equivalent “candidate configurations“ can be obtained by rotating and flipping an initial configuration. In presence of random process variation, any of them has equal opportunity to be selected as the optimal implementation for a specific FPGA chip. If each individual from a large number of FPGAs is applied with the optimal among all candidate configurations, the overall timing performance is evidently improved compared to applying a single configuration to those FPGAs. Furthermore, the technique of LE swapping makes faster one of two neighboring LEs occupied by critical paths, which guarantees an incremental timing performance improvement based on any optimized design. Twenty MCNC benchmark circuitsare placed and routed by VPR [12]. Statistical timing performance is obtained by Monte-Carlo simulation with FPGA process variation model. The experimental results demonstrate evident timing yield improvement. Compared to previous VAD works, the proposed method saves the effort of variation characterization and design time. / Although process variation is always stated as a side-effect, it still offers some opportunities for variation-based applications. The invention of physically unclonable function (PUF) enlightens the researchers to translate physical uniqueness to digital identification. In the third part of this thesis, a compact chip identification (ID) circuit on FPGA is presented. An array of ring oscillators is used to measure the process variation. The chip ID is calculated based on their relative speeds. The repeatability of chip ID generation is a common challenge for all kinds of implementations, particularly when variations in operating conditions such as supply voltage and temperature are taken into account. To address this issue, configurable ring oscillators together with an orthogonal (re-)initialization scheme is used to improve reliability. The implementation of the proposed design is tested on nine Xilinx Spartan-3e FPGA chips. The experimental results show that the new method significantly enhances reliability of ID generation and tolerance to environmental changes. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yu, Haile. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 125-137). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract --- p.ii / Acknowledgement --- p.vi / Publication List --- p.viii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Introduction to Process Variation --- p.1 / Chapter 1.2 --- Variation Compensation --- p.3 / Chapter 1.2.1 --- Post-silicon Tuning --- p.3 / Chapter 1.2.2 --- Variation-Aware Design (VAD) --- p.5 / Chapter 1.3 --- Background and Prior Art --- p.6 / Chapter 1.3.1 --- Variation Characterization --- p.6 / Chapter 1.3.2 --- Variation Compensation --- p.8 / Chapter 1.3.3 --- Chip Identification --- p.11 / Chapter 1.4 --- Motivations --- p.17 / Chapter 1.4.1 --- Variation Characterization --- p.17 / Chapter 1.4.2 --- Timing Yield Improvement by Architectural Symmetry --- p.18 / Chapter 1.4.3 --- Chip Identification --- p.18 / Chapter 1.5 --- Key Contributions --- p.19 / Chapter 1.5.1 --- Variation Characterization --- p.19 / Chapter 1.5.2 --- Timing Yield Improvement by Architectural Symmetry --- p.20 / Chapter 1.5.3 --- Chip Identification --- p.20 / Chapter 1.6 --- Thesis Outline --- p.22 / Chapter 2 --- Variation Characterization for FPGA --- p.24 / Chapter 2.1 --- Introduction --- p.25 / Chapter 2.2 --- Characterization Primitives --- p.27 / Chapter 2.3 --- Methodology --- p.28 / Chapter 2.3.1 --- LE Characterization --- p.30 / Chapter 2.3.2 --- LUT Full Characterization --- p.33 / Chapter 2.3.3 --- Interconnect Characterization --- p.36 / Chapter 2.4 --- Implementation --- p.39 / Chapter 2.5 --- Experimental Results --- p.41 / Chapter 2.5.1 --- Scaling Factor --- p.41 / Chapter 2.5.2 --- Characterization Results --- p.42 / Chapter 2.5.3 --- Verification --- p.47 / Chapter 2.6 --- Conclusion and Discussion --- p.49 / Chapter 2.6.1 --- Discussion --- p.50 / Chapter 3 --- Timing Yield Improvement for FPGA --- p.51 / Chapter 3.1 --- Introduction --- p.52 / Chapter 3.2 --- Variation Model --- p.52 / Chapter 3.2.1 --- Random Variation --- p.53 / Chapter 3.2.2 --- Spatial Correlation --- p.54 / Chapter 3.3 --- Theoretical Analysis --- p.55 / Chapter 3.3.1 --- 1-out-of-N Redundancy Method --- p.55 / Chapter 3.3.2 --- Configuration-Level Redundancy vs. Fine-Grained Adjustment --- p.57 / Chapter 3.3.3 --- Coverage Rate of Fine-Grained Adjustment --- p.61 / Chapter 3.4 --- Architecture --- p.62 / Chapter 3.4.1 --- Modification for Configuration Rotation and Flip --- p.62 / Chapter 3.4.2 --- Modification for Fine-grained Adjustment --- p.65 / Chapter 3.5 --- Flow of Methodology --- p.66 / Chapter 3.6 --- Experimental Results --- p.68 / Chapter 3.7 --- Cost-Efficiency Comparison --- p.74 / Chapter 3.8 --- Conclusions --- p.76 / Chapter 4 --- Chip Identification Circuit for FPGA --- p.78 / Chapter 4.1 --- Introduction --- p.79 / Chapter 4.2 --- Design --- p.80 / Chapter 4.2.1 --- Measurement Circuits --- p.80 / Chapter 4.2.2 --- “Cell“ Composition and One-bit Generation --- p.82 / Chapter 4.3 --- Results --- p.85 / Chapter 4.3.1 --- Distribution of R[subscript i] --- p.86 / Chapter 4.3.2 --- Effect of P,T,N --- p.87 / Chapter 4.3.3 --- Distribution of 1’s and 0’s --- p.88 / Chapter 4.3.4 --- Hamming Distance --- p.89 / Chapter 4.3.5 --- Execution Time --- p.89 / Chapter 4.3.6 --- Variation with Temperature --- p.90 / Chapter 4.4 --- Conclusions --- p.93 / Chapter 5 --- Enhanced Chip Identification Circuit for FPGA --- p.96 / Chapter 5.1 --- Introduction --- p.96 / Chapter 5.2 --- Sources of Instability --- p.97 / Chapter 5.3 --- Implementation --- p.98 / Chapter 5.3.1 --- Overlapped Cell Composition --- p.98 / Chapter 5.3.2 --- Configurable RO --- p.99 / Chapter 5.3.3 --- Configuration Initialization --- p.101 / Chapter 5.3.4 --- Flow of Chip ID Generation --- p.107 / Chapter 5.4 --- Results --- p.109 / Chapter 5.4.1 --- Summary of Hardware Resource Consumption --- p.109 / Chapter 5.4.2 --- Statistical Analysis --- p.109 / Chapter 5.4.3 --- Environmental Influences --- p.117 / Chapter 5.5 --- Conclusion --- p.119 / Chapter 6 --- Conclusion --- p.120 / Chapter 6.1 --- Future Work --- p.122 / Chapter 6.1.1 --- Variation Characterization for FPGA --- p.122 / Chapter 6.1.2 --- Timing Yield Improvement for FPGA --- p.123 / Chapter 6.1.3 --- Chip Identification Circuit for FPGA --- p.124 / Bibliography --- p.137

"Theoretical modeling, design, assembly, and measurement of a novel integrated phased array radiator are presented. The droopy bowtie turnstile radiator with quad line feed meets challenging radar requirements and uses low cost manufacturing and assembly techniques. This thesis develops the complete theoretical model (antenna, balun, feeding network) of a broadband phased array radiator: the droopy bowtie turnstile radiator. A novel quad line balun feed is developed that provides a low loss, high isolation, and coincident phase-center feeding network for the droopy bowtie. The radiator and feed design combines broadband RF performance and high-isolation dual-linear polarization in a low profile, compact package that enables wide scan volume performance versus frequency. This thesis develops low-cost manufacturing and assembly techniques applied to the droopy bowtie radiator with the quad line feed. The new radiator design would utilize low cost fabrication techniques such as injection molding and 3-D printing, and also leverages automated assembly techniques. Measurement prototypes and array prototypes of droopy bowtie radiators with the quad line feed are developed for L- and X-bands. The measurements demonstrate broadband RF performance in a low profile compact package viable for wide-scale phased array applications."

abstract: Modern computer systems are complex engineered systems involving a large collection of individual parts, each with many parameters, or factors, affecting system performance. One way to understand these complex systems and their performance is through experimentation. However, most modern computer systems involve such a large number of factors that thorough experimentation on all of them is impossible. An initial screening step is thus necessary to determine which factors are relevant to the system's performance and which factors can be eliminated from experimentation. Factors may impact system performance in different ways. A factor at a specific level may significantly affect performance as a main effect, or in combination with other main effects as an interaction. For screening, it is necessary both to identify the presence of these effects and to locate the factors responsible for them. A locating array is a relatively new experimental design that causes every main effect and interaction to occur and distinguishes all sets of d main effects and interactions from each other in the tests where they occur. This design is therefore helpful in screening complex systems. The process of screening using locating arrays involves multiple steps. First, a locating array is constructed for all possibly significant factors. Next, the system is executed for all tests indicated by the locating array and a response is observed. Finally, the response is analyzed to identify the significant system factors for future experimentation. However, simply constructing a reasonably sized locating array for a large system is no easy task and analyzing the response of the tests presents additional difficulties due to the large number of possible predictors and the inherent imbalance in the experimental design itself. Further complications can arise from noise in the system or errors in testing. This thesis has three contributions. First, it provides an algorithm to construct locating arrays using the Lovász Local Lemma with Moser-Tardos resampling. Second, it gives an algorithm to analyze the system response efficiently. Finally, it studies the robustness of the analysis to the heavy-hitters assumption underlying the approach as well as to varying amounts of system noise. / Dissertation/Thesis / Masters Thesis Computer Engineering 2018

Ziel der Arbeit war es, dichte Neuronenkulturen in kleinere Untereinheiten zu unterteilen, welche durch ihre Neuriten miteinander in Kontakt standen. Zu diesem Zweck wurden auf MEAs zellbindende Kreisareale mittels Mikrostempeltechnik auf die zellabweisende Schicht aus Polyethylenglykol übertragen. Dudurch wurde gewährleistet, dass scharf abgegrenzte Neuronenareale für mehrere Wochen auf dem MEA wuchsen und nach Ausbildung der neuritischen Verbindungen untereinander, die elektrische Aktivität zwischen den Kreiskammern gemessen werden könnte. Das sollte Auskunft über Informationsausbreitung in Neuralnetzen geben und die Theorien über Synchronität und Synfirechains prüfbar machen. / It was the aim, to prodruce dense neural cultures and subdivide them into smaller units, which could communicate with each other via their neurites. For that purpose cell-friendly circular areals (PECM) were printed onto the MEA surface covered by a thin layer of Star-PEG. That should garantee that the cells grow in sharp-lined neuronal circles, that would grow for several weeks on the chip and that after they would have spread their neurites their electrical actions between the circles could be measured. That could provide future information about the synchronized spread of neural information.

Perturbation techniques are useful in the design of low complexity adaptive antenna arrays for estimating the gradient required in stochastic descent algorithms. Implementing projected perturbation sequences in an adaptive array allows the simultaneous reception of signals and the adaptation of the array weights while preserving the constraints imposed on the array weights.This thesis quantifies the performance of narrowband adaptive array processors that employ projected perturbation techniques. For different perturbation receiver structures the performance is determined under idealised conditions and importantly also when practical implementation issues are taken into account.The arrays performance is characterised by analysing the transient performance of the weight covariance matrix and by determining the misadjustment. By drawing similarities between two established analysis techniques a new misadjustment analysis technique is introduced.Practical implementation can impact on the arrays performance such that the benefit of the projected perturbation approach is lost. By characterising the array's sensitivity to perturbation noise additional projections which counteract some implementation effects are identified. The level of loss of performance due to weight quantisation and the limited dynamic range of the array weights is determined.

This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.

Addendum inserted / Includes bibliography / vii, 114 leaves, [11] leaves of plates : ill. (some col.) ; 31 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.)--Mawson Institute for Antarctic Research, University of Adelaide, 1987