International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / As technology progresses we are faced with ever increasing volumes and rates of raw and processed telemetry data along with digitized high resolution video and the less demanding areas of video conferencing, voice communications and general LAN-based data communications. The distribution of all this data has traditionally been accomplished by solutions designed to each particular data type. With the advent of Asynchronous Transfer Modes or ATM, a single technology now exists for providing an integrated solution to distributing these diverse data types. This allows an integrated set of switches, transmission equipment and fiber optics to provide multi-session connection speeds of 622 Megabits per second. ATM allows for the integration of many of the most widely used and emerging low, medium and high speed communications standards. These include SONET, FDDI, Broadband ISDN, Cell Relay, DS-3, Token Ring and Ethernet LANs. However, ATM is also very well suited to handle unique data formats and speeds, as is often the case with telemetry data. Additionally, ATM is the only data communications technology in recent times to be embraced by both the computer and telecommunications industries. Thus, ATM is a single solution for connectivity within a test center, across a test range, or between ranges. ATM can be implemented in an evolutionary manner as the needs develop. This means the rate of capital investment can be gradual and older technologies can be replaced slowly as they become the communications bottlenecks. However, success of this evolution requires some planning now. This paper provides an overview of ATM, its application to test ranges and telemetry distribution. A road map is laid out which can guide the evolutionary changeover from today's technologies to a full ATM communications infrastructure. Special applications such as the support of high performance multimedia workstations are presented.

Siu Chun. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 66-68). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Thesis Overview --- p.3 / Chapter 2 --- Background and Related work --- p.4 / Chapter 2.1 --- Emergence of IP-over-ATM --- p.4 / Chapter 2.2 --- ATM architecture --- p.5 / Chapter 2.3 --- Scheduling issues in output-queued switch --- p.6 / Chapter 2.4 --- Scheduling issues in input-queued switch --- p.18 / Chapter 3 --- The Deadline-ordered Burst-based Parallel Scheduling Strategy --- p.23 / Chapter 3.1 --- Introduction --- p.23 / Chapter 3.2 --- Switch and queueing model --- p.24 / Chapter 3.2.1 --- Switch model --- p.24 / Chapter 3.2.2 --- Queueing model --- p.25 / Chapter 3.3 --- The DBPS Strategy --- p.26 / Chapter 3.3.1 --- Motivation --- p.26 / Chapter 3.3.2 --- Strategy --- p.31 / Chapter 3.4 --- The Deadline-ordered Burst-based Parallel Iterative Matching --- p.33 / Chapter 3.4.1 --- Algorithm --- p.34 / Chapter 3.4.2 --- An example of DBPIM --- p.35 / Chapter 3.5 --- Simulation results --- p.33 / Chapter 3.6 --- Discussions --- p.46 / Chapter 3.7 --- Future work --- p.47 / Chapter 4 --- The Quasi-static DBPIM Algorithm --- p.50 / Chapter 4.1 --- Introduction --- p.50 / Chapter 4.2 --- Quasi-static path scheduling principle --- p.51 / Chapter 4.3 --- Quasi-static DBPIM algorithm --- p.56 / Chapter 4.4 --- An example of Quasi-static DBPIM --- p.59 / Chapter 5 --- Conclusion --- p.63 / Bibliography --- p.65

Since the emergence of the Asynchronous Transfer Mode ( A TM ) concept, various switching architectures have been proposed. The multistage interconnection networks have been proposed for the switching architecture under the A TM environment. In this thesis, we propose a new model for the performance analysis of an A TM switching fabric based on single-buffered Banyan network. In this model, we use a three-state, i.e., "empty", "new" and "blocked" Markov chain model to describe the behavior of the buffer within a switching element. In addition to traditional statistical analysis including throughput and delay, we also examine the delay variation. Performance results show that the proposed model is more accurate in describing the switch behavior under uniform traffic environment in comparison with the "two-state" Markov chain model developed by Jenq, et. al.[4] [6] . Based on the "three-state" model, we study a packet priority scheme which gives the blocked packet higher priority to be routed forward during contention. It is found that the standard deviation of the network delay is reduced by about 30%.

Mobile communications are becoming integrated into society at an explosive rate. While 2nd generation (2G) systems limit the user to basic services such as voice and low-bit rate data, 3G networks are characterized by their ability to accommodate wideband multi-media traffic with Quality of Service (QoS) guarantees. In the design of a system the Medium Access Control (MAC) layer is responsible for multiplexing heterogeneous traffic onto a common transmission link and its design is critical to the overall performance of a system. A number of MAC protocols for wireless networks have been proposed in the literature - the majority having time division multiple access (TDMA) at the MAC layer. However in 3G systems there is a trend towards the use of code division multiple access (CDMA) due to its proven advantages in a wireless environment. Although several papers on CDMA based MAC protocols have been published, virtually none of them tackle the analysis aspect of the protocols. Those papers that do perform analyses of CDMA protocols don't often consider heterogeneous traffic, and even fewer support QoS. The thesis addresses these shortcomings by proposing a MAC protocol that supports QoS in the form of Bit Error Rate (BER) and packet delay guarantees. The thesis begins by giving an overview of proposed wireless ATM and 3G CDMA protocols and then details how power control may be used to support BER guarantees. Various Markov based analyses are presented along with Monte-Carlo Simulations. An Equilibrium Point Analysis is then performed and the work discusses how such analyses are generally infeasible for systems supporting heterogeneous traffic. After an overview of conventional scheduling algorithms the thesis proceeds to outline a novel approach by which delay guarantees may be offered using packet dropping rates as the QoS metric. Using a stochastic source model as opposed to the conventional leaky bucket traffic regulator the thesis diverges significantly from conventional literature. The thesis also details how to calculate the probability of QoS violation and concludes with suggestions on further research avenues. As a whole the work is unique in its approach to analyse heterogeneous traffic and the methods it uses to construct session admission zones for QoS guarantees. / Thesis (Ph.D.)-University of Natal,Durban, 2002.

Der Asynchronous Transfer Mode (ATM) stellt die zukünftige und einheitliche Basistechnologie für das Breitband-ISDN dar. Da nahezu alle wesentlichen Protokollfunktionen in Hardware realisierbar sind, soll nachfolgend ein Überblick über bereits angebotene VLSI-Schaltkreise gegeben werden. Eine Systematisierung und Einordnung vorhandener ATM-Chips hinsichtlich ihrer Leistungsfähigkeit und ihres Funktionsumfangs erfolgt in Hinblick auf das sogenannte B-ISDN-Referenzmodell. Dieses Schichtenmodell definiert die notwendigen Protokolle und Schnittstellen für den Asynchronous Transfer Mode. Zum grundlegenden Verständnis wird einleitend eine kurze Einführung in die Basisprinzipien von ATM gegeben.

Αντικείμενο της διατριβής είναι η επίδειξη μεθόδων, που βρίσκουν εφαρμογή, τόσο ειδικότερα στην σχεδίαση πολύπλοκων ψηφιακών μικροηλεκτρονικών κυκλωμάτων μεγάλης ταχύτητας, για τηλεπικοινωνιακά δίκτυα οπτικών ινών, όσο και γενικότερα για την επίλυση θεμάτων χρονισμού, που προκύπτουν κατά την υλοποίηση πολύπλοκων ολοκληρωμένων συστημάτων πάνω σε chip. Όσον αφορά, τον χώρο των τηλεπικοινωνιακών κυκλωμάτων, παρουσιάζονται μέθοδοι, τόσο για την συνολική οργάνωση του ολοκληρωμένου κυκλώματος, όσο και για την κυκλωματική υλοποίηση λειτουργικών μονάδων κοινών σε τηλεπικοινωνιακά κυκλώματα, με απαιτήσεις υψηλής ταχύτητας, χαμηλής κατανάλωσης, και ταυτόχρονης συνύπαρξης πολλαπλών ρολογιών. Η επίδειξη των προτεινόμενων μεθόδων καθώς και η επαλήθευση της ορθότητά τους, πραγματοποιείται, μέσα από την υλοποίηση σε πυρίτιο, ενός πολύπλοκου τηλεπικοινωνιακού ολοκληρωμένου κυκλώματος, με υψηλές απαιτήσεις ταχύτητας λειτουργίας. Όσον αφορά, τον γενικότερο χώρο της σχεδίασης πολύπλοκων ολοκληρωμένων System-on-Chip (SoC), παρουσιάζονται μέθοδοι για την επίλυση προβλημάτων χρονισμού, στα σύγχρονα ψηφιακά ολοκληρωμένα κυκλώματα, που σχετίζονται με την διάδοση και τον πολλαπλασιασμό της συχνότητας του ρολογιού, στο εσωτερικό των κυκλωμάτων αυτών. Πιο συγκεκριμένα, παρουσιάζονται μέθοδοι που μπορούν να εφαρμοστούν, τόσο για την εξάλειψη της παρέκκλισης, μεταξύ των κόμβων των εσωτερικών ρολογιών, όσο και για την εξάλειψη της παρέκκλισης μεταξύ εξωτερικού και εσωτερικού ρολογιού, στα ολοκληρωμένα κυκλώματα. Όσον αφορά το δεύτερο, η συχνότητα του εσωτερικού ρολογιού δεν ταυτίζεται απαραίτητα με αυτήν του εξωτερικού, αλλά επιτρέπεται να έχει πολλαπλάσια τιμή από αυτήν. Για την ευθυγράμμιση του εσωτερικού με το εξωτερικό ρολόι, προτείνεται η συστηματική μέθοδος LCD-SMD, η οποία είναι κατάλληλη για χρήση σε ολοκληρωμένα όπου επικρατούν συνθήκες μακρύ οδηγού ρολογιού, παράγει εσωτερικό ρολόι πολλαπλάσιο του εξωτερικού με σταθερό 50% duty-cycle, έχει μικρό χρόνο κλειδώματος, και χρησιμοποιεί εξ’ ολοκλήρου ψηφιακές λογικές πύλες. Η επικύρωση της ορθότητας των προτεινόμενων μεθόδων για θέματα χρονισμού, γίνεται κατά ένα μέρος με υλοποίηση σε πυρίτιο, και κατά ένα άλλο μέρος με εξομοιώσεις. / This Thesis aims to demonstrate design methods that can be applied as much in the design of high complexity, high speed, digital integrated circuits for optical fiber networks, as more generally to resolve timing issues, arising during the implementation of integrated circuits (IC’s). Specifically, in this Thesis we present methods for the holistic organization of a digital integrated circuit (driven by the needs imposed by nowadays telecommunications area), as well as methods regarding circuit implementation of various common functional units in telecommunications circuits that require high speed, low power and multiple clocks. The proposed methods are demonstrated and validated through the silicon implementation of a complex telecom integrated circuit (SDH framer). The design of the here-above mentioned chips lie into the more general area of the complex integrated Systems-on-Chips (SoCs). The methods developed in the Thesis, concern the distribution and frequency multiplication of the clock signal, inside the chip. In particular, we address between others, methods to remove the skew between the internal clock nodes, as well as methods to remove the skew between the internal and external clock. The internal clock frequency is allowed to be a multiple of the external clock frequency. For the alignment of the internal with the external clock, the systematic open-loop method LCD-SMD has been proposed, which is applicable to IC’s with long clock driver conditions. Through this method, we accomplish the generation of an internal clock with multiple frequencies than the external, while preserving a constant 50% duty-cycle. The method results into a fast lock time, and employs only standard digital logic gates. The proposed methods are validated both by silicon implementation and by simulations.

The growth of Asynchronous Transfer Mode (ATM) was considered to be the ideal carrier of the high bandwidth applications like video on demand and multimedia e-learning. ATM emerged commercially in the beginning of the 1990's. It was designed to provide a different quality of service at a speed up 100 Gbps for both real time and non real time application. The turn of the 90's saw a variety of technologies being developed. This project analyzes these technologies, compares them to the Asynchronous Transfer Mode and assesses the future of ATM.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.