Thanks to the booming of car electronics in recent years, more car electronics devices are installed in ve-hicles. These devices are connected by in-vehicle communication networks. In this thesis, we present the tran-sceiver and clock generator design for the physical layer of a FlexRay-based in-vehicle communication protocol. Regarding the transceiver design, a LVDS-like transmitter is proposed to drive the twisted pair of the bus. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition at the re-ceiver end. The reliability and safety are the priority design factors for electronics. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation, a sub-1 MHz oscillator, and a temperature detector are included in our clock generator design. All of these designs are implemented by using a typical 0.18 um single-poly six-metal CMOS process. The proposed prototypical transceiver has been tested by a thermo chamber to justify its operation in the required temperature rage, i.e., -40¢XC to 125¢XC. Moreover, the compatibility of our design is also verified in a real FlexRay-based network. The maximum throughput of the proposed prototypical transceiver can reach 40 Mbps.

Three different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a transimpedence preamplifier for 16 Mbps infrared transceiver modules. The design of the preamplifier is aimed at the VFIR (very fast infrared) which is supposed to provide a 16 Mbps data transmission rate. The second topic is focused on the implementation of a robust reference clock generator design for DDR synchronous devices. A pulse generator circuit to generate pulses corresponding to the rise edges and fall edges of a given clock is presented. The third topic is to carry out a cost-effective voice dialer. It focuses on the voice feature extraction and the recognition of Chinese numbers 0 to 9. We present a low-cost method to implement such an algorithm by using 8051-ICE.

With the increasing system clock, a clock circuit will cause an amount of electromagnetic interference. To reduce EMI of the products, various EMI strategies have been developed. In the thesis, we study the suppression of electromagnetic interference of a clock circuit by using the spread spectrum technique. The basic idea of the spread spectrum is to slightly modulate the frequency of the clock signal and the energy of the signal will be dispersed to a controllable range to reduce the peak energy of each harmonic wave in the spectrum, and the products can pass the electromagnetic compatibility test more easily. We obtain the attenuation factor of spread spectrum from the theoretical derivation, including modulation index and modulation profiles. From the numerical simulation, we verify that spread spectrum technique can suppress the peak energy. We propose the attenuation formulas which can control the attenuation of every frequency point. To verify our findings, we use a spread spectrum clock generator from market to perform measurement. The trapezoidal waveform can be used to represent a clock circuit. Its waveform includes rise time and duty cycle. We will discuss the influence of rise time and duty cycle on the spread spectrum technique. Shorter rise time will cause high order harmonics in the high speed clock circuit. We verify that spread spectrum technique can suppress high order harmonics from both the simulation and experiment. Because every harmonic can be suppressed, the spread spectrum technique has the good suppression effect for the whole system.

This thesis includes two topics. The first topic is a low power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter (DAC) used in an implantable neural stimulator. An ANT-based low-power 8-bit pipelining carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Both the added power-aware clock control circuit and clock generation circuit detecting data transition take advantage of shutting down the processing stages given identical inputs in two consecutive operations by keeping high clock level. The design keeps the advantage of high speed while having the effect of low power dissipation. The implantable neural stimulator assists patients to reconstruct transmission paths of neural signals by current stimulation. The proposed small DAC not only decreases the chip area and power dissipation by reducing transistor count, but also improves the linearity with higher current output performance. All of measured performances of the proposed DAC make the chip worthy of being implemented in a field application.

This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.

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This thesis includes three topics. The first topic is a low-variation 1 MHz clock generator. The second one is a high sensitivity linear voltage-to-frequency converter. The last one is a high-PSR bias circuit for NTSC SYNC separation. All of the circuits can be applied to related consumer electronic products. The low-variation 1 MHz clock generator includes a bias circuit which automatically compensates the drifting caused by temperature variations. Furthermore, the circuit contains neither BJTs nor diodes to reduce the area cost. The frequency variation is measured to be less than 2.55\% in the range of 0¢J~90¢J. The high sensitivity linear voltage-to-frequency converter is mainly constructed by a window comparator[11]. We analyze and improve the performance of accuracy to achieve both high accuracy and high sensitivity. The accuracy error is less than 1% and sensitivity is 84 KHz/V in the voltage range of 0.1V~0.8V. The high-PSR bias circuit for NTSC SYNC Separation is implemented by a bandgap reference which is controlled by a feedback loop to reduce the interference of the environment. The measurement variation of the bandgap reference is less than 1\% when the variation of power supply is 10\%. The sensitivity of the bandgap reference to temperature is measured to be 0.0006V/¢J.

¡@¡@The first topic of this thesis is a high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage when the design is implemented by TSMC (Taiwan Semiconductor Manufacturing Company) 0.35um CMOS 1P4M technol- ogy. ¡@¡@The second topic of this thesis is an 1-to-4 joystick enhanced interface which can be attached to SONY PS2 (playstation 2) is developed. The enhanced interface can allow 4 persons to play simultaneously through one port at the original game console. A total of 8 players can be supported when two of the interfaces hook up with both joystick ports of the console. The multiple player entertainment effect can be drastically enhanced by the usage of such an interface.

This thesis focuses on problem-solution analysis of synchronous digital circuits; the results of which are autosynchronous circuit design methodology, timing parameter definitions based on simulation models and constraint settings. The RTL transformation of the synchronous state machine in VHDL language to an autosynchronous state machine was created with minimal modifications for the simple design of these circuits. Following this, a comparison of the transformed state machines with their synchronous originals in parameters such as chip area, current consumption and timing specification domain is introduced. The summation of this thesis displays a theoretical comparison of several types of synchronization (synchronous, autosynchronous, fundamental asynchronous, EAIC, Bundled-data, Dual-rail) which are presented on the single state machine example with the same technology parameters.

<p>This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. </p><p>It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. </p><p>This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. </p><p>The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.</p>