This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.

Αντικείμενο της διατριβής είναι η επίδειξη μεθόδων, που βρίσκουν εφαρμογή, τόσο ειδικότερα στην σχεδίαση πολύπλοκων ψηφιακών μικροηλεκτρονικών κυκλωμάτων μεγάλης ταχύτητας, για τηλεπικοινωνιακά δίκτυα οπτικών ινών, όσο και γενικότερα για την επίλυση θεμάτων χρονισμού, που προκύπτουν κατά την υλοποίηση πολύπλοκων ολοκληρωμένων συστημάτων πάνω σε chip. Όσον αφορά, τον χώρο των τηλεπικοινωνιακών κυκλωμάτων, παρουσιάζονται μέθοδοι, τόσο για την συνολική οργάνωση του ολοκληρωμένου κυκλώματος, όσο και για την κυκλωματική υλοποίηση λειτουργικών μονάδων κοινών σε τηλεπικοινωνιακά κυκλώματα, με απαιτήσεις υψηλής ταχύτητας, χαμηλής κατανάλωσης, και ταυτόχρονης συνύπαρξης πολλαπλών ρολογιών. Η επίδειξη των προτεινόμενων μεθόδων καθώς και η επαλήθευση της ορθότητά τους, πραγματοποιείται, μέσα από την υλοποίηση σε πυρίτιο, ενός πολύπλοκου τηλεπικοινωνιακού ολοκληρωμένου κυκλώματος, με υψηλές απαιτήσεις ταχύτητας λειτουργίας. Όσον αφορά, τον γενικότερο χώρο της σχεδίασης πολύπλοκων ολοκληρωμένων System-on-Chip (SoC), παρουσιάζονται μέθοδοι για την επίλυση προβλημάτων χρονισμού, στα σύγχρονα ψηφιακά ολοκληρωμένα κυκλώματα, που σχετίζονται με την διάδοση και τον πολλαπλασιασμό της συχνότητας του ρολογιού, στο εσωτερικό των κυκλωμάτων αυτών. Πιο συγκεκριμένα, παρουσιάζονται μέθοδοι που μπορούν να εφαρμοστούν, τόσο για την εξάλειψη της παρέκκλισης, μεταξύ των κόμβων των εσωτερικών ρολογιών, όσο και για την εξάλειψη της παρέκκλισης μεταξύ εξωτερικού και εσωτερικού ρολογιού, στα ολοκληρωμένα κυκλώματα. Όσον αφορά το δεύτερο, η συχνότητα του εσωτερικού ρολογιού δεν ταυτίζεται απαραίτητα με αυτήν του εξωτερικού, αλλά επιτρέπεται να έχει πολλαπλάσια τιμή από αυτήν. Για την ευθυγράμμιση του εσωτερικού με το εξωτερικό ρολόι, προτείνεται η συστηματική μέθοδος LCD-SMD, η οποία είναι κατάλληλη για χρήση σε ολοκληρωμένα όπου επικρατούν συνθήκες μακρύ οδηγού ρολογιού, παράγει εσωτερικό ρολόι πολλαπλάσιο του εξωτερικού με σταθερό 50% duty-cycle, έχει μικρό χρόνο κλειδώματος, και χρησιμοποιεί εξ’ ολοκλήρου ψηφιακές λογικές πύλες. Η επικύρωση της ορθότητας των προτεινόμενων μεθόδων για θέματα χρονισμού, γίνεται κατά ένα μέρος με υλοποίηση σε πυρίτιο, και κατά ένα άλλο μέρος με εξομοιώσεις. / This Thesis aims to demonstrate design methods that can be applied as much in the design of high complexity, high speed, digital integrated circuits for optical fiber networks, as more generally to resolve timing issues, arising during the implementation of integrated circuits (IC’s). Specifically, in this Thesis we present methods for the holistic organization of a digital integrated circuit (driven by the needs imposed by nowadays telecommunications area), as well as methods regarding circuit implementation of various common functional units in telecommunications circuits that require high speed, low power and multiple clocks. The proposed methods are demonstrated and validated through the silicon implementation of a complex telecom integrated circuit (SDH framer). The design of the here-above mentioned chips lie into the more general area of the complex integrated Systems-on-Chips (SoCs). The methods developed in the Thesis, concern the distribution and frequency multiplication of the clock signal, inside the chip. In particular, we address between others, methods to remove the skew between the internal clock nodes, as well as methods to remove the skew between the internal and external clock. The internal clock frequency is allowed to be a multiple of the external clock frequency. For the alignment of the internal with the external clock, the systematic open-loop method LCD-SMD has been proposed, which is applicable to IC’s with long clock driver conditions. Through this method, we accomplish the generation of an internal clock with multiple frequencies than the external, while preserving a constant 50% duty-cycle. The method results into a fast lock time, and employs only standard digital logic gates. The proposed methods are validated both by silicon implementation and by simulations.

This project focus to desing an on-chip oscillator in function as a clock generator. Frequency stability of the oscillator is affected by supply voltage, temperature and process variations. The aim is to propose a clock generator with sufficient frequency stability, low power consumption and a small chip area. This work deals with the types of oscillators and their basic building blocks suitable for our application. It also deals with the study and design options of temperature and process compensation circuit generating the current control, which provides the frequency stabilization of the output signal.

This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.

<p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p>