The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping to meet the current needs of SoCs is the integration of larger memory with the processor, and with this, comes the challenge of testing all the memory cells. The programmable memory BIST offers a flexible approach to designers and testers because it allows the memory test algorithms to be updated when new memory fault models are discovered. But this flexibility comes as a trade-off to area as the BIST circuitry needs to be integrated next to the memory array. This report proposes enhancements to an existing design that will improve flexibility by enhancing the address generation schemes while simultaneously eliminating the need for an auxiliary memory in cases where a Type-1 NPSF background will be used. A comparison of the base design to the proposed design shows the address and data generation improvements can be achieved with only 1.8% increase in area with an 8KB memory. / text

In this project we evaluated the perception of speedin a driving simulator. The study provides a preliminary survey that focuses onhow human beings can perceive moving in space. We have developed and implemented some techniques to study how we modify the perception of speed in adriving simulator. We targeted the driving perspective, trying to create certain effects in order to affect the perceived sense of speed. Changing the contrast of the scene we studied how the perception of the speed has been modified. Testing this modification we saw a change in the perception of the speed by the driver, who noticed an increase of the perceived speed through the alteration of the contrast of the scene.