The thesis Data transmission error-protection with BCH codes deals with a large class of random-error correcting cyclic codes which are able to protect binary data and can be used for example in data storages, high speed modems. Bose, Chaudhuri and Hocquenghem (BCH) codes operate over algebraic structures called Galois fields. The BCH encoding is the same as cyclic encoding and can be done with linear feedback shift register but decoding is more complex and can be done with different algorithms - in this thesis there are two algorithms for decoding Peterson and Berlekam-Massey mentioned. The aim of this thesis is to find BCH code which is able to correct t = 6 independent errors in up to data sequence n = 150 bits, then peruse possible realizations of the codecs and set criteria for the best realization, then design and test this realization. This thesis is split into three main parts. In the first part there are encoding and decoding methods of the BCH code generally described. The second part deals with selecting of the right code and realization. There was chosen BCH (63,30) code and realization with FPGA chip. In the last part is described design of BCH encoder and decoder and compilation in the Altera design software.

This work involves in anti-error coding systems with interleaving. At first is given summary of high-frequency use error correction codes. Below there are described two basic techniques of interleaving and their confrontation. The next text is focusing on survey and characteristics of codes which conform to submission. After selection of optimal system is verified its function in MATLAB environment. Final step is creation of functional application in C++ environment. This application serves to transmission of error correction BMP pictures.

The work deals with data security using BCH codes. In the work are described BCH codes in binary and non-binary form, and their most important subclass RS codes. Furthermore, this work describes the method of decoding Peterson-Gorenstein-Zierl, Berlekamp- Massey and Euclidean algorithm. For the presentation of encoding and decoding process, the application was created in Matlab, which has two parts – Learning BCH codes and Simulation of BCH codes. Using the generated application performance of BCH codes was compared at the last part of the work.

Digital image watermarking has developed for the purpose of protecting intellectual property rights to multimedia data. The focus of this thesis is searching for an alternative solution of digital image watermarking methods. A detailed analysis of watermarking methods particularly in the frequency domain, and the modification of these methods are the main aim of this work. Improved performance in watermark extraction is one of the main goals. First, the common static image watermarking methods, possible attacks on the watermarked data and techniques for objective measurement of watermarked image quality are shortly introduced. Techniques which use the space domain for watermarking ar described in the next part of this work. It is about techniques which insert the watermark into the least significant bits of an image both in the RGB domain and in the YUV domain. The main part of the thesis depicts modified and newly developed static image watermarking methods in the frequency domain. These methods use various transforms and error-correction codes, by means of which the watermark robustness increases. All the methods developed are tested in MATLAB. Results together with tables and graphs are one part of work. The end of the thesis is devoted to a comparison of all the developed methods and their evaluation.

Thesis (MSc (Mathematics))--University of Stellenbosch, 2006. / The main topic of this thesis is the construction of the algebraic geometric codes (Goppa codes), and their decoding by the list-decoding, which allows one to correct beyond half of the minimum distance. We also consider the list-decoding of the Reed–Solomon codes as they are subclass of the Goppa codes, and the determination of the parameters of the non primitive BCH codes. AMS Subject Classification: 4B05, 94B15, 94B35, 94B27, 11T71, 94B65,B70. Keywords: Linear codes, cyclic codes, BCH codes, Reed–Solomon codes, list-decoding, Algebraic Geometric codes, decoding, bound on codes, error probability.

<p>The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation.</p><p>This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard.</p><p>The system is written in VHDL and is intended for implementation on an FPGA.</p>

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation. This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA.

Αντικείμενο της διπλωματικής εργασίας αποτελεί η μελέτη και ανάλυση των μεθόδων διόρθωσης λαθών με χρήση κώδικα BCH που μπορούν να εφαρμοστούν σε συστήματα αποθήκευσης πληροφορίας τεχνολογίας PCM (Phase-Change Memory). Η τεχνολογία PCM αποτελεί μία νέα τεχνολογία που υπόσχεται υψηλές χωρητικότητες, χαμηλή κατανάλωση ισχύος και μπορεί να εφαρμοστεί είτε σε συσκευές αποθήκευσης σταθερής κατάστασης (Solid State Drives) είτε σε μνήμες τυχαίας προσπέλασης (Random-Access Memories), παρέχοντας μία εναλλακτική πρόταση έναντι μνημών τεχνολογίας flash και DRAM. Ένα από τα μειονεκτήματα της τεχνολογίας PCM είναι η ανθεκτικότητα εγγραφής (write endurance), η οποία μπορεί να βελτιωθεί με τη χρήση μεθόδων διόρθωσης λαθών που θα παρατείνουν τον χρόνο ζωής της συσκευής όταν, λόγω της φυσικής φθοράς του μέσου, αρχίσουν να υπάρχουν σφάλματα στα αποθηκευμένα δεδομένα. Για την εφαρμογή της διόρθωσης λαθών μπορούν να χρησιμοποιηθούν κώδικες BCH, οι οποίοι αποτελούν μια κλάση ισχυρών κυκλικών κωδίκων διόρθωσης τυχαίων λαθών, και κατασκευάζονται με χρήση της άλγεβρας πεπερασμένων πεδίων. Οι κώδικες BCH είναι ιδανικοί για διόρθωση λαθών σε συσκευές αποθήκευσης πληροφορίας όπου η κατανομή των λαθών είναι τυχαία. Αρκετοί αλγόριθμοι έχουν προταθεί για τις λειτουργίες αποδοτικής κωδικοποίησης και αποκωδικοποίησης κωδίκων BCH. Στην παρούσα εργασία μελετήθηκαν λύσεις που μπορούν να υλοποιηθούν με παράλληλες αρχιτεκτονικές, ενώ ειδικότερα για την λειτουργία αποκωδικοποίησης έγινε χρήση ενός παράλληλου αλγορίθμου που δεν χρειάζεται αντιστροφείς πεπερασμένου πεδίου για την επίλυση των εξισώσεων των συνδρόμων, επιτυγχάνοντας υψηλές συχνότητες λειτουργίας. Για την κατανόηση των λειτουργιών κωδικοποίησης και αποκωδικοποίησης απαιτείται η προσεκτική μελέτη της άλγεβρας πεπερασμένων πεδίων και της αριθμητικής της. Οι κώδικες BCH προσφέρουν πλεονεκτήματα όπως χαμηλή πολυπλοκότητα και ύπαρξη αποδοτικών μονάδων υλοποίησης σε υλικό. Στην παρούσα εργασία σχεδιάστηκαν ένας παράλληλος κωδικοποιητής και ένας παράλληλος αποκωδικοποιητής για τον κώδικα BCH(728,688). Τα δύο συστήματα υλοποιήθηκαν ως περιφερειακά σε ενσωματωμένο σύστημα βασισμένο σε επεξεργαστή MicroBlaze, με έμφαση σε μια καλή σχέση μεταξύ της συχνότητας λειτουργίας και των απαιτήσεων σε επιφάνεια υλικού και κατανάλωση ισχύος. Για την υλοποίηση χρησιμοποιήθηκε συσκευή FPGA σειράς Virtex-6. / The objective of this thesis is the study and analysis of BCH error-correction methods that can be applied on PCM (Phase-Change Memory) storage devices. PCM is a new technology that promises high capacities, low power consumption and can be applied either on Solid State Drives or on Random Access Memories, providing an alternative to flash and DRAM memories. However, PCM suffers from limited write endurance, which can be increased using error-correction schemes that will extend the lifetime of the device when, due to medium wear-out, errors start to appear in the written data. Thus, BCH codes (powerful cyclic random multiple error-correcting codes) can be employed. BCH codes are ideal for ECC (Error-Correction Coding) in storage devices, due to their fault model which is random noise. Several algorithms have been proposed for the efficient coding and decoding BCH codes. In the present thesis parallel implementations where studied. For the decoding process in particular, a parallel algorithm was used that does not require finite field inverter units to solve the syndrome equations, achieving high operation frequencies. For the understanding of BCH coding and decoding processes, basic knowledge of the finite field algebra and arithmetic is required. BCH codes offer advantages such as low complexity and efficient hardware implementations. In the present thesis a parallel BCH(728,688) encoder and a parallel BCH(728,688) decoder were designed. The above systems were implemented as peripherals on an MicroBlaze-based embedded system, with emphasis on an optimal tradeoff between area and power consumption. A Virtex-6 FPGA device was used for the final stages of the implementation.

The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper describes a 300 Mega Bit Per Second (MBPS) Front End Processor (FEP) prototype completed in early 1993. The FEP implements a patent pending parallel frame synchronizer (frame sync) design in 12 Actel 1240 Field Programmable Gate Arrays (FPGA's). The FEP also provides (255,223) Reed-Solomon (RS) decoding and a High Performance Parallel Interface (HIPPI) output interface. The recent introduction of large RAM based FPGA's allows greater high speed data processing integration and flexibility to be achieved. A proposed FEP implementation based on Altera 10K50 FPGA's is described. This design can be implemented on a single slot 6U VME module, and includes a PCI Mezzanine Card (PMC) for a commercial Fibre Channel or Asynchronous Transfer Mode (ATM) output interface module. Concepts for implementation of (255,223) RS and Landsat 7 Bose-Chaudhuri-Hocquenghem (BCH) decoding in FPGA's are also presented. The paper concludes with a summary of the advantages of high speed data processing in FPGA's over Application Specific Integrated Circuit (ASIC) based approaches. Other potential data processing applications are also discussed.