This thesis presents a comprehensive assessment of breakdown and operational voltage constraints in state-of-the-art silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS technology. Technology scaling of SiGe HBTs for high frequency performance results on lower breakdown voltages, making operating voltage constraints an increasingly vital reliability consideration in SiGe HBTs from both a device and circuits perspective.

Home medical equipment becomes increasingly popular as VLSI fabrication technology advances. However, there are two important factors for realizing a miniaturized biochip: low noise [1] and low power. Firstly, physiological signals are very susceptible to interference while the amplitude of the signal is only a few millivolts or less. If the circuit cannot reject noise effectively, it is hard to amplify the signal and obtain the output voltage of the recording system accurately. Secondly, it is not convenient to replace the batteries frequently when using the portable measurement instrument for the patients. This thesis is focused on the measurement of physiological signals, such as electrocardiography (ECG) [2], electroneurogram (ENG) [3] and electromyography (EMG) [4] , and designing an all-in-one recording system to measure the different physiological signals in a chip. For this purpose, a programmable multi-parameter system for recording of the wide range of physiological signals is designed. The system provides two types of input transconductance stages, BiCMOS and CMOS. BiCMOS amplifiers provide high gain , low noise [5] and low offset voltage suitable for the small amplitude of the physiological signal. On the other hand, CMOS amplifiers provide practically infinite input impedance and ultra-low leakage current. The system also provides three selectable amplifier modes: (a) double-differential amplifier, (b) single-differential amplifier in channel 1, (c) single-differential amplifier in channel 2. The double-differential amplifier provides a high common-mode rejection and adjustable gain for each channel to further reduce common-mode interference. The single-differential amplifier (channel 1 or channel 2) in the recording system are also accessible as differential-input and single-ended output channels. Moreover, the system provides an offset compensation structure to prevent the amplifier from exceeding the input range. The offset compensation system can selectively be turned off to reduce the power consumption.

<p>Detecting small signals with a comparator demands that the total voltage offset is lower than the actual signal. The total offset includes the voltage offset in the comparator and the voltage offset that is created by the offset currents that flows thru the load at the comparators input. The goal with this comparator that has been developed has been that it will have a total voltage offset at maximum 500 uV. The comparator does not need to be extremely fast or does not need to operate in a big frequency area. To have all the flexibility that is needed a full custom technique is used. When the mismatch is most unfavourable the total offset is 209.24 uV which is within the goal.</p> / <p>För att kunna detektera små signalnivåer med en komparator krävs att den har en lägre total spänningsoffset än den signalnivå den skall detektera. I den totala offseten ingår dels den rena spänningsoffseten i komparatorn och dels den spänningsoffset som kommer att skapas när offsetströmmar på komparatorns ingångar går igenom den last som finns på ingången. Målet med den komparator som utvecklats har varit att den skall ha en total spänningsoffset på maximalt 500 uV. Inga direkta krav såsom att den skall vara snabb och att den skall kunna arbeta inom ett stort frekvensområde finns. För att få den flexibilitet som behövs är komparatorn konstruerad i en så kallad full custom teknik. När missanpassningen är som mest ogynnsam hamnar den totala spänningsoffseten på 209.24 uV vilket ligger inom målet med god marginal.</p>

Zugl.: Berlin, Techn. Univ., Diss., 2009

Zugl.: Ilmenau, Techn. University, Diss., 2006.

Thanks to a small wavelength (large bandwidth) combined with a low loss transmission window around 94 GHz and 120 GHz, the 75-120 GHz frequency band in millimeter wave (mm-wave) provides a promising opportunity for high data rate long range wireless communications and high-resolution imaging systems. Large-scale phased arrays have been exploited in such application for their beam forming and null steering capabilities, resulting in high directivity and improved SNR. But growing DC power consumption (Pdiss) in such large scale arrays has become an on-going concern along with noise, linearity and phase resolution trade-offs in current phased array architectures. To address these issues, we propose a power efficient phase shifter (PS) architecture based on quadrature hybrid coupler, which leverages the benefits of conventional active and passive PSs at mm-wave. The phase shifter has low loss, resulting in low power dissipation and the power domain phase interpolation by the quadrature hybrid gives low phase error and high linearity. We design W-band (90-100 GHz) phased array transmit and receive (T/R) modules in 130 nm SiGe BiCMOS technology based on the proposed PS and our measurements show high power efficiency with the lowest power consumption at W-band to our knowledge (18mW and 26mW power dissipations at receiver (Rx) and transmitter (Tx) front-ends respectively). Rx shows 23 to 25 dB peak gain, 6 to 9.3 dB NF and Tx can deliver upto 7 dBm output power with 18% power efficiency. Moreover, our PS can achieve 5-bit phase resolution with <2 degrees RMS phase error and provides 0 dBm saturated output power at 94 GHz. The phase shifter (PS) is also scalable beyond W-band without significant loss. We demonstrate this with a 120 GHz two channel phased array receiver (Rx), where a single channel shows 15.6 dB peak gain with Pdiss=53 mW which shows one of the highest gain efficiency (gain/Pdiss) among D-band phased arrays. We can further reduce the power consumption by leveraging the bidirectional signal processing at the phased array front-end. To achieve this, we designed a W-band bidirectional variable gain amplifier with gain variation ranging from 6 to -1 dB at 94 GHz which can be used along with bidirectional PS. The amplifier will replace the lossy SPDT switch in the conventional bidirectional approach, reducing the overall power consumption. / Ph. D. / The wireless technology is pushing towards the high operating frequencies to achieve high data rate and 75-120 GHz frequency band in millimeter wave (mm-wave) are of great current interest for the backhaul communications, radar and imaging systems. However, high frequency yields high propagation loss which has been overcome with large scale phased arrays in such applications for their high directivity, narrow beam forming capabilities and implementation with silicon technologies. The high dissipation due to large number of elements is a major concern which often requires heat sinks around the sensors leading to increase in cost, size and weight. For the large silicon array to be of practical use in commercial systems, it is paramount to maintain a high power efficiency and low power dissipation in the array element. In this research, a power efficient phased array architecture has been proposed which is implemented to design transmit/receive (T/R) modules in advanced silicon technologies. Experimental results show that the proposed architecture achieves the lowest power consumption and improved power efficiency per T/R element among state-of-the-art mm-wave phased arrays. The research also proposes an alternative way to improve power efficiency of phased arrays by reusing the amplifiers in both transmit and receive path where the amplifier replaces lossy switch as well, resulting in a low loss bidirectional system which can reduce the power consumption further. Finally, we believe that this research contribution has an significant impact in the effort of building low power large-scale phased arrays at mm-wave frequencies.

Le travail réalisé au cours de cette thèse porte sur l’optimisation du transistor bipolaire à hétérojonction Si/SiGe:C pour les applications d’amplification de puissance pour les communications sans fils. Nous présentons tout d’abord la structure d’étude. Il s’agit du transistor bipolaire à hétérojonction Si/SiGe:C intégré en technologie BiCMOS 0.25µm sur plaques 200mm. La cellule dédiée à l’amplification de puissance est présentée. Une attention particulière est apportée aux phénomènes thermiques inhérents à ce type de cellules ainsi qu’aux solutions mises en œuvre pour les atténuer. Les diverses optimisations réalisées sur l’architecture du TBH sont détaillées. Ces optimisations touchent à la fois à la modification du procédé technologique et au dessin du transistor. Notre étude porte sur l’amélioration des performances petit et grand signal via l’optimisation des paramètres technologiques définissant la structure épitaxiale intrinsèque de base et de collecteur ainsi que des règles de dessin du transistor. Enfin, deux types d’architectures de TBH développées sont présentées. L’une de type simple polysilicium quasi auto-alignée qui s’intègre dans une technologie dédiée à l’amplification de puissance, l’autre présentant une structure double polysilicium également auto-alignée. / The present work deals with Si/SiGe:C heterojonction bipolar transistor optimization for power amplifier applications dedicated to wireless communications. We first present the investigated structure, a Si/SiGe:C heterojonction bipolar transistor integrated in a 0.25µm BiCMOS technology on 200 mm wafers. We discuss the cell dedicated to power amplification. We have paid attention to thermal phenomenon linked to this kind of cell and to possible dedicated solutions. Various optimizations realized on HBT architecture are detailed. These optimizations concern technological process modifications and transistor design. The main objective of this work is to improve both large and small signal characteristics. This is obtained by transistor design rule variations, collector and base intrinsic parameters optimization. Finally, two kind of developed HBT architectures are presented. One, simple polysilicium quasi self aligned, integrated in a technology dedicated to power amplification, the other one fully self aligned with double polysilicium structure.

Ce travail porte sur la conception d'un amplificateur de puissance à 79 GHz et la co-intégration de l'amplificateur de puissance et l'antenne en technologie silicium SiGe. L'objectif de la thèse est de développer un module radiofréquence à l'émission pour des applications radar à 79 GHz. Ce module sera composé d'un amplificateur de puissance, d'une antenne et du circuit d'adaptation PA/Antenne. L'inter-étage entre le PA et l'antenne est une source supplémentaire d'atténuation du signal, d‟autant plus rédhibitoire en technologie intégrée pour des fréquences aussi élevées. En réalisant une conception commune, ou co-design, de l'antenne et de l'amplificateur de puissance (PA), nous pouvons, à terme, nous affranchir du traditionnel inter-étage d'adaptation d'impédance entre ces deux blocs. Plus précisément, il convient de dimensionner l'antenne afin qu'elle présente a la sortie du PA l'impédance optimale que requiert son rendement en puissance maximum. / This work focuses on the design of a power amplifier (PA) at 79 GHz and the co-integration of the PA and the antenna on SiGe technology. The objective of this thesis is to develop a RF front-end block for radar applications at 79 GHz. This block is compound of a power amplifier, antenna and PA/Antenna inter-stage matching. The inter-stage between the PA and the antenna adds supplementary losses in the global performances, especially prohibitive in integrated technology for high frequencies. The co-design of the antenna and the PA allows to suppress the traditional inter-stage impedance matching between these two blocks. More specifically, it is suitable to design the antenna with the appropriate output impedance of the PA which gives optimal performances for maximum power and efficiency.

L'objectif de cette thèse est de démontrer la faisabilité d'oscillateurs contrôlés en tension (O.C.T.) rivalisant en termes de bruit de phase avec les O.C.T. fabriqués en technologies III V. Cet O.C.T. doit être complètement intégré, adresser la bande Ku et utiliser la technologie QUBiC4X de NXP Semiconductors. Les travaux de cette thèse sont articulés autour de trois chapitres principaux, le premier revient sur les bases fondamentales à la compréhension des phénomènes inhérents aux composants électroniques et présents dans les oscillateurs plus particulièrement. Le second explique, en s'appuyant sur l'analyse des formes d'ondes et sur des calculs analytiques, les choix retenus en termes d'architecture pour la partie active ainsi que pour le résonateur afin de minimiser la conversion du bruit AM/PM et atteindre les meilleures performances possibles en bruit de phase. Il décrit les quatre versions d'O.C.T. réalisés et analyse les résultats de simulations post-layout obtenus pour justifier leur fabrication. Il présente notamment une architecture innovante utilisant les avantages d'un montage cascode ainsi qu'un résonateur à trois inductances différentielles imbriquées les unes dans les autres. Le troisième chapitre détaille les choix de design faits lors du dessin des masques ainsi que les résultats de mesures obtenus pour les quatre versions fabriquées. Enfin, il se termine par une énumération des recherches menées dans le but d'expliquer les différences observées entre les résultats de mesure et de simulation. / The thesis goal is to demonstrate the feasibility of voltage controlled oscillator (VCO) challenging the VCOs using III-V technologies regarding phase noise performances. This VCO must be fully integrated, target the Ku-band and use the QUBiC4X process from NXP Semiconductors. This thesis work is based on three main chapters, the first one reviews the fundamentals to understand the intrinsic phenomena in electronics components and more particularly in oscillators. The second explains, by using the waveforms analysis and analytical demonstrations, the choices made regarding both the active part and the resonator architecture in order to minimize the AM/PM noise conversion and then to reach the best phase noise performances. It describes the four versions of the realized VCOs and analyzes the post-layout simulations results to justify their fabrications. It shows more specifically an innovative architecture using the advantages of a cascode configuration and a resonator based on three interlocked differential inductors. Finally, the third chapter focuses on the masks' layout and measurements results of the four VCOs. It also details the investigations made to explain the differences between measurements and simulations.

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Tables