In this thesis, some most popular technologies for both resonator and active device were presented and compared. Two MMIC VCOs were selected to design on InGaP HBT and push push configuration with different topologies, namely balanced Colpitts and balanced Clapp. Optimization factors which give significant contribution to lower phase noise were investigated, such as Q factor, current density, bias circuitry, feedback capacitor ratio and etc. The optimum simulation results were obtained in the end of this work, which have the lowest phase noise such as -119.6 ~ -122.2 dBc/Hz (f0) with more than 16% tuning range and -108.7 ~ -111.2 dBc/Hz (f0) with 10% tuning range at 100 kHz offset frequency, respectively. The results were also analyzed by the formula of FOMT, which were -191.01 dBc/Hz and -182.48 dBc/Hz, respectively. The phase noise performance can reach the state of the art level and indicate potential applications.

Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial ATA(SATA) and Fibre channel standard applications. Among all these applications, clock data recovery (CDR) is one of the key design components. With the increasing demand for higher bandwidth and high integration, Complementary metal-oxidesemiconductor (CMOS) implementation is now a design trend for the predominant products. In this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in standard 0.18 μ m CMOS is developed. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate the required zero and poles and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1.The implementation is the first fully integrated 10Gb/s CDR IC which meets/exceeds the SONET standard in the literature. The second proposed CDR architecture includes an adaptive bang-bang control algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang CDR. The main contribution of the proposed architecture is that it optimizes the loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady state jitter of the CDR, which leads to an improved jitter tolerance performance. According to simulation, the jitter performance is improved by more than 0.04UI,which alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre channel/Sonet Standard.

This thesis introduces a multipass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.

In the early 1980s and 1990s, the first- and second-generation networks in wireless communication, called 1G and 2G, were introduced with only limited data connectivity in the world. The former could only transfer voices while the latter could transfer voices and messages. By the early 2000s, however, the 3G networks began working and let people have real access to the internet. The greater functionality enabled by 4G networks evolved from increased demand for higher data rates in the early 2010s. Nowadays, we are totally engaged in 4G world of LTE (Long Term Evolution) owing to the eruptive increase of mobile internet in smart phones or other mobile devices. The 5G networks are categorized into two branches according to their frequencies: (i) sub-6 GHz (700 MHz to 6 GHz) and (ii) near-millimeter wave (25 to 30 GHz). Commonly used applications are included in the sub-6 GHz, also called the Internet-of-Everything (IoE) and Internet-of-Things (IoT). To fulfill the date rate required for 5G applications, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption. The main objective of this thesis is to carry out research on a fully integrated analog PLL fractional-N frequency synthesizer for 5G wireless communication and IoE/IoT applications in sub-6 GHz. To do this, we have studied the trends in the research of LC-VCOs (voltage-controlled oscillators) and identified the methods for going towards a low flicker-noise corner. Then, we have implemented the designed LC-VCO which is the main noise source in PLLs. In the final step we have designed the sub-blocks of the fractional-N analog frequency synthesis. The sub-blocks have been optimized to have less power dissipations. The implementation of a fully integrated analog PLL fractional-N frequency synthesizer is done in 180-nm standard CMOS technology (TSMC). It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz. The phase noise at 10KHz varies between -94 dBc/Hz to -115dBc/Hz. / Thesis / Doctor of Philosophy (PhD) / The data rate in wireless, cellular communications, and wireline keeps growing by nearly 10 times per 5 years. To fulfill such date rate, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption. This dissertation aims to implement an ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE/IoT applications in 180-nm standard CMOS technology (TSMC). An analog PLL is used in this frequency synthesizer.

Fully integrated Ultra-Wideband (UWB) RFIC transmitters are designed in Si-based technologies for applications such as wireless communications or sensor networks. UWB technology offers many unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks and frequency mixing with single sideband mixers ----- are explored in great detail. To generate the required UWB signals, pulse generators are designed and integrated into the transmitter chips. The first prototype UWB transmitter is designed in Freescale Semiconductor 0.18μm SiGe BiCMOS technology for operation over three 500 MHz bands at center frequencies of 4.6/6.4/8.0 GHz, and generates pulses supporting differential BPSK modulation. The transmitter output frequency is controlled by a two-bit code which sets the state of a switched capacitor tank array for coarse tuning of the VCO. While selecting between the different bands, the transmitter is capable of settling and re-transmitting in less than 0.7μs using an integrated, wide band phase-locked loop (PLL). Various issues such as mismatch/inaccuracy of the pulses and high power consumption of the prescaler were identified during the first design and were addressed in subsequent design revisions. The pulse generator is a critical part of the proposed UWB transmitter. The initial pulse generator design used CMOS delay lines and logic gates to synthesize the required pulse bandwidth; however this approach suffered from inaccurate pulse timing control due to delay time sensitivity to device modelling and process variations. Subsequently, a novel pulse generator design capable of achieving accurate timing control was implemented using digital logic and a fixed oscillator frequency to provide timing information, integrated into a modified transmitter circuit, and subsequently fabricated in Jazz Semiconductor's 0.18μm CA18 RFCMOS process. Experimental results confirm the generation of accurate one-nanosecond pulses. Finally, a new multiband UWB transmitter based on a new single sideband (SSB) resistive mixer with superior linearity and zero static power consumption was also designed and fabricated using Jazz CA13 0.13μm RF CMOS process. This design is based on a fixed frequency phase-locked VCO and generates different bands through frequency mixing. In the prototype design, two additional carrier frequencies are generated from the VCO center frequency (5 GHz) by mixing it with its output divided-by-4 (1.25 GHz). By switching the relative I/Q phases of the LO/IF inputs to this single side band mixer, either the upper side band (6.25 GHz) or lower side band (3.75 GHz) frequency is selected at the mixer output, while the other sideband is rejected. Simulation results show that the transmitter is capable of generating the desired carrier frequencies while suppressing the image component by more than 40 dB. Overall, this work has explored various aspects of UWB transmitter design and implementations in fully integrated silicon chips. The major contributions of this work include: proposed hardware architectures for pulse-based multiband UWB transmitters; implemented a fully integrated multiband UWB transmitter with embedded phase-locked switched-tank VCO capable of wide frequency tuning; demonstrated an all digital pulse generator capable of generating accurate one-nanosecond pulse trains in the presence of various mismatches; and investigated resistive SSB mixer topologies and their implementation in a multiband UWB generation architecture. / Ph. D.

Le sujet de cette thèse porte sur la réalisation d'un bloc de transposition de fréquence de 1 à 20GHz à base de composants MEMS. Cette thèse s'est traduite par la conception et la réalisation d'un nouveau type de capacité MEMS RF variable, qui se base sur des structures rotatives de type gyroscope pour l'actionnement, et sur une variation de surface pour la variation de capacité. Comparée à différentes architectures publiées à ce jour, cette structure a l'avantage d'avoir la partie actionnement (la partie MEMS) et la partie RF (la capacité) isolées électriquement, ce qui permet d'éviter le phénomène d'auto actionnement avec la puissance du signal RF traversant. Un autre avantage de la structure développée est la possibilité d'avoir simultanément 8 capacités variables sur une puce unique, avec un seul système d'actionnement. La fabrication de ces puces nécessite l'utilisation d'un wafer SOI pour la partie MEMS et d'un wafer en verre pour la partie RF, ce qui offre la possibilité d'une mise en boitier du MEMS directement pendant le procédé de fabrication. Ces travaux ont également porté sur l'étude du phénomène de pullin dans le cadre des peignes interdigités incurvés (curved combdrive), laissant apparaître les paramètres physiques critiques lors du dimensionnement. Cette étude paramétrique a été utilisée pour améliorer la structure d'actionnement en utilisant des peignes interdigités à largeur de doigt et à gap variable, pour repousser ce phénomène de pullin en dehors de la plage utile d'actionnement. Cette nouvelle capacité variable a ensuite été intégrée dans un système simple d'oscillateur accordable sur alumine pour valider ses performances RF et pourra être associée à un mélangeur pour réaliser le bloc complet de transposition de fréquence / This thesis deals with the realisation of a frequency transposition block from 1 to 20 GHz based on MEMS components. It results in the design and fabrication of a new kind of tuneable RF MEMS capacitor based on a rotational gyroscope structure for the actuation part and on a surface variation for the capacitance change. Compared to other architectures published, this structure presents the advantage to have an actuation part (the MEMS part) and a RF part (the capacitor) that are electrically separated in order to avoid the phenomenon of self-actuation with RF signal crossing power. Another advantage of this structure is the possibility to simultaneously tune 8 different capacitors on a single chip, with only one actuation system. The fabrication of the chips requires the use of a SOI wafer for the MEMS part and a glass wafer for the RF part, which offers on chip packaging opportunity. This work also focused on the study of the pull-in effect in the case of curved comb-drives, highlighting the most critical physical parameters for the design. This parametric study has been used to improve the actuation structure and more particularly the topology of the curved comb-drives by variation of the finger width and gap. These modifications were done in order to push the pull-in effect out of the actuation operating range. This new tuneable capacitor has been integrated into a simple VCO circuit on alumina to validate the RF performances and could be associated to a RF mixer in order to realize the full frequency transposition block

Quadrature LO signal is a key element in many of the RF transceivers which tend to dominate today’s wireless communication technology. The design of a quadrature LC VCO with better phase noise and lower power consumption forms the core of this work. This thesis investigates a coupling mechanism to implement a quadrature voltage controlled oscillator using indirect injection method. The coupling network in this QVCO couples the two LC cores with their super-harmonic and it recycles its bias current back into the LC tank such that the power consumed by the coupling network is insignificant. This recycled current enables the oscillator to achieve higher amplitude of oscillation for the same power consumption compared to conventional design, hence assuring better phase noise. Mathematical analysis has been done to study the mechanism of quadrature operation and mismatch effects of devices on the quadrature phase error of the proposed QVCO. The proposed quadrature LC VCO is designed in TSMC 0.18 μm technology. It is tunable from 2.61 GHz - 2.85 GHz with sensitivity of 240 MHz/V. Its worst case phase noise is -120 dBc/Hz at 1 MHz offset. The total layout area is 1.41 mm^2 and the QVCO core totally draws 3 mA current from 1.8 V supply.

The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the design costs, etc. The functioning of an all-digital ADC is based on the time domain signal processing approach, which brings a high time resolution obtained by the use of a nanometer CMOS process. An all-digital ADC design is implemented by using a combination of the digital Voltage-Controlled Oscillator (VCO) and a Time-to-Digital Converter (TDC). The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. In addition, the VCO works as a time based quantizer. The time-based signal from the VCO output is then processed by the TDC quantizer in order to generate the digital code sequences. The fully digital VCO-based ADC has the advantage of superior time resolution. Moreover, the VCO-based ADC offers a first order noise shaping property of its quantization noise. This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter. The circuit level simulations have been done in Cadence Virtuoso ADE. A multi-phase VCO and multi-bit quantization architecture has been chosen for this 8-bit ADC. The power consumption of the ADC is approximately 630 μW at 1.0 V power supply and the figure of merit is around 410 fJ per conversion step.

In this thesis, the design of a scaling-friendly continuous-time closed-loop voltage controlled oscillator (VCO) based Delta-Sigma analog to digital converter (ADC) is introduced. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly operational transconductance amplifiers (OTAs) and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses digital to analog converter (DAC) mismatches. The prototype ADC in 130 nm complementary metal-oxide-semiconductor (CMOS) occupies a small area of 0.03 mm² and achieves 66.5 dB signal to noise and distortion ratio (SNDR) over 2 MHz bandwidth (BW) while sampling at 300 MHz and consuming 1.8 mW under a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respectively. / text

This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the deep submicron region, the voltage-domain-based ADCs begins to suffer in improving their performance due to the use of complex analog components. A promising solution to improve the performance of an ADC is to employ as many as possible digital components in a time-domain-based ADC, where it uses the time resolution of an analog signal rather than the voltage resolution. In comparison, as the CMOS process scales down, the time resolution of an analog signal has found superior than the voltage resolution of an analog signal. In recent years, such time-domain-based ADCs have been taken an immense interest due to its inherent features and their design reasons. In this thesis work, the VCO-based ADC design, falls under the category of time-based ADCs which consists of a VCO and an appropriate digital processing circuitry. The employed VCO is used to convert a voltage-based signal into a time signal and thereby it also acts as a time-based quantizer. Then the resulting quantized-time signal is converted into a digital signal by an appropriate digital technique. After different architecture exploration, a conventional VCO-based ADC architecture is implemented in a high-level model to understand the characteristic behaviour of this time-based ADC and then a comprehensive functional schematic-level is designed in reference with the implemented behavioural model using cadence design environment. The performance has been verified using the mixed-levels, of transistor and behavioural-levels due to the greater simulation time of the implemented design. ADC’s dynamic performance has been evaluated using various experiments and simulations. Overall, the simulation experiments showed that the design was found to reach an ENOB of 4.9-bit at 572 MHz speed of sample per second, when a 120 MHz analog signal is applied. The achieved peak performance of the design was a SNR of 40 dB, SFDR of 34 dB and an SNDR of 31 dB over a 120 MHz BW at a 1 V supply voltage. Without any complex building blocks, this VCO-based all-digital ADC design provided a key feature of inherent noise shaping property and also found to be well compatible at the deep submicron region.