Tato práce se zabývá návrhem výkonového měniče určeného pro použití ve fotovoltaických systémech. Klíčovým je použití programovatelného hradlového pole (FPGA) pro realizaci řídicích funkcí. Do detailu jsou diskutovány aspekty návrhu spínaných měničů a na základě takto získaných poznatků je zkonstruován funkční vzorek měniče.

The delivery of high power and smaller footprints through a non-isolated topology demands for the use of multiphase topology in DC-DC converters. Multiphase reduces the ripple observed on both the input and output waveforms; however, it may not be enough to connect to sensitive power sources such as renewable energy sources. A single-phase modified boost converter demonstrates the ability to acquire very minimal input current ripple by addition of passive components. The expansion to multiphase topology is the next logical step for higher power application while furthering the low input current ripple benefit. In this thesis, the multiphase modified boost topology is compared with the multiphase standard boost topology to explore the benefits and trade-offs of the proposed topology. A 12V input to 19V output at 95W output power multiphase standard and modified boost converters were designed and constructed for the thesis. Results from theoretical calculations, computer simulations, and hardware implementations were then compared to evaluate their performances. Results show that compared to the standard boost, the modified boost yields significantly less input current ripple at 2% under full load condition while maintaining output voltage ripple of 5% and higher than 90% efficiency.

No description available.

With the rapid evolving IT technologies, today, the power factor correction (PFC) design is facing many challenges, such as power scalability, high entire-load-range efficiency, and high power density. Power scalability is a very desirable and cost-effective approach in the PFC design in order to keep up with servers' growing power requirements. Higher power density can eventually reduce the converter cost and allows for accommodating more equipment in the existing infrastructures. Driven strongly by economic and environmental concerns, high entire-load-range efficiency is more and more required by various organizations and programs, such as the U.S. Energy Star, Climate Savers, and German Blue Angel. Today, the existing boost PFC is reaching its limitations to meet these challenges simultaneously. Using the cutting-edge semiconductor devices, further efficiency improvement at light load is still needed. There are limited approaches available for increasing the power density due to the large EMI filter and inductor size. Interleaved multi-channel boost PFC is a promising candidate to meet those challenges, but the interleaved boost converter is a less explored area. On the other hand, the multi-channel interleaved buck converter for the VR application has been intensively studied and thoroughly explored. One basic approach of this study is trying to extend the existing knowledge and techniques obtained from multiphase buck converters to the multi-channel interleaved boost converters since there are similarities existed between the multi-phase buck and the multi-channel boost converters. The existing studies about the interleaving impact on the EMI filter design are based on the time domain ripple cancellation effect. This approach is good enough for most of the filter designs. However, unlike the conventional filter designs, the EMI filter design is a specification related process. Both the EMI standard and the EMI measurement are based on the frequency domain spectrum. Limited by the existing analysis approaches, it is difficult to provide a clear picture about how exactly the multi-channel interleaving will impact the EMI filter design. The interleaving impact on the Common Mode (CM) noise also has not been studied in any existing literatures for the same reason. In this study, the frequency domain analysis method was adopted. With the double Fourier integral transformation, a closed-form expression of all the harmonics of the noise sources can be obtained. With all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, the multi-channel interleaving impact on both the differential mode (DM) and CM filter design can be clearly understood and summarized. According to the design curves provided, the EMI filter size can be effectively reduced by properly choosing the interleaving channel number and the switching frequency. The multi-channel interleaving impact on the output capacitor current ripple is also studied and summarized in this dissertation. It should be pointed out that interleaving only reduces the total input and output current ripples; the inductor current in each channel still has large ripple if small inductance is used. Similar to the multi-phase buck converter, coupling inductors result in different equivalent inductances for input current ripple and inductor current ripple for boost converters. Keeping the inductor current ripple magnitude the same, inverse coupling inductors between the interleaved channels can reduce the inductor size. However, the DM filter size is increased due to larger input current. Based on the investigation on the total magnetic component weight, inverse coupling inductor can reduce the total magnetic component weight. The reduction is more pronounced for lower switching frequency design when the inductor size is dominating among the total magnetic components. Based on the harmonic cancellation, and with all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, a novel phase angle control method is proposed to maximize the reduction of the EMI filter. For example, in a 2-channel interleaved PFC, just by changing the interleaving scheme to 90 degree phase shift, 39% total volume reduction of the EMI filter can be achieved. The proposed phase angle controlled multi-channel PFC is experimentally demonstrated and verified on a digital controlled 4-channel PFC. The phase angle control method proposed in the multi-channel boost converter can be applied back to the multi-phase buck converter as well. The harmonic cancellation principle will be the same as the multi-channel boost converter. The same benefits can be obtained when the requirement is defined in the frequency domain, e.g. the EMI Standard. The interleaved multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. However, shedding phases can reduce the ripple cancellation effect as well, which will result in the EMI noise increase and losing the benefit on the EMI filter. By applying the proposed phase-shedding with phase angle control strategy, the phase shedding impact on the EMI filter design can be minimized. The light load efficiency can be improved without compromising the EMI filter size. Then, adaptive frequency controlled PFC is proposed to further improve the PFC light load efficiency. The proposed light load efficiency improvement strategies are combined and implemented on the platform of the digital controlled 4-channel PFC. The benefit of improving the light load efficiency is experimentally verified. The EMI performance is also evaluated with the EMI measurement results obtained from the PFC prototype. Following the same approach explored, the benefits of interleaved boost converter can be further extended other applications, such as the boost converter in the Hybrid Electric Vehicles (HEV) and photovoltaic (PV) system. / Ph. D.

The continuous conduction mode (CCM) boost, buck-boost and buck-boost derived pulse-width modulation dc-dc converters suffer from the large-signal control-to-output nonlinearity. Without feedback control, the large-signal control-to-output nonlinearity would lead to output overregulation and even damage the components. The control gain is defined as the ratio of output voltage to control signal. The small-signal control gain is defined as differentiating output voltage with respect to control signal. Feedback control helps to make the output trace the reference signal. A large-signal control-to-output linearity is established. Compared with open loop control, the feedback loop design is complex; and the feedback control might suffer from the instability caused by the negative small-signal control gain, which is due to the loss and parasitic in practice. Except feedback control, open loop linearization methods can also realize the large-signal control-to-output linearity. A modulated-ramp pulse-width modulation generator is introduced in [6]. A current source works as the control signal. A capacitor is charged by the current source, whose voltage works as the carrier and compared with a constant dc bias voltage to determine the duty cycle. When applying this method to boost, buck-boost and buck-boost derived PWM dc-dc converters, a large-signal control-to-output linearity is established. However, the control gain is dependent on the input voltage; it cannot maintain constant when input voltage varies. A feedforward pulse width modulator is introduced in [39] to realize a large-signal control-to-output linearity. The static conversion ratio is divided into numerator and denominator as the functions of duty cycle. An integrator with reset clock signal helps to determine the right timing. The control gain is ideally constant and independent of input voltage. However, the mismatch between the integrator time constant and the switching period would result in a nonlinear control gain, which is dependent on the input voltage. In the thesis work, a self-oscillating unified linearizing modulator is introduced. It first provides a unified procedure to establish a large-signal control-to-output linearity for different pulse-width modulation dc-dc converters. Feedforward is employed to mitigate the impact from line voltage. Self-oscillation is adopted to provide the internal clock signal and to determine the switching frequency. A constant control gain is obtained, independent on the input voltage or the mismatch between clock signals. The modulator is constructed by three simple and standard building blocks. With the considerations of parasitic components and loss, how to design the constant gain, which excludes the negative small-signal control gain within the entire control signal range, is analyzed and discussed. The performance of this self-oscillating unified linearizing modulator is verified by experiments. The impacts from propagation delay in practical components are taken into considerations, which improves the quality of generated signals. Combined with a boost converter, a good large-signal control-to-output linearization is demonstrated. In the future work, the small-signal control-to-output transfer function is first deduced based on the SOUL modulator. Bode plots show the unique characteristic based on the SOUL modulator compared with the conventional modulator. Next, the impacts from this unique characteristic to feedback loop design and dynamic performance are discussed. / Master of Science

In the fast growing field of Telecommunications, the back up DC power supply plays a vital role in powering the telecom equipment. This DC power supply is a combination of AC-DC Rectifier coupled with a battery bank to support the load when AC input is not available. Figures 0.1 and 0.2 show the line diagram of the DC power supply. The power supply is the most critical element in a telecom installation and it should be highly reliable in order to have un-interrupted service. (Fig) Besides reliability, power density and cost are the driving forces behind the success of a power supply in the market. Off late, the reach of telecom in the society is very wide covering remote villages and major metros. Given this environment, the power supply is exposed to extreme input conditions. It is desirable to design the power supply capable of withstanding wide AC input conditions. Another advantage is that the rectifier unit will keep the battery charged so that the battery will have long life. This thesis is aimed at designing a 1400W (56V/25A) telecom power supply, keeping in view of the issues expressed above. The aim is to design a Switched Mode Rectifier (SMR) that tolerate wide input voltage variations (90Vac to 300Vac). In addition, the design covers unity input power factor, high efficiency (> 90%), high power density ( ), parallel operation and low cost ( ). Chapter 1 of this thesis covers the context and motivation of the work. Chapter 2 presents the design issues pertaining to power supplies. The normalized description of the power converters is presented. Such a description enables one to compare several circuit topologies in order to make effective design decisions. In a similar way the effectiveness of the switches and mgnetics are presented to enable design decisions in the output stage of the rectifier. Chapter 3 presents the design of the 1400W telecom power supply, keeping in view of the stated specifications. The performance results of the converter are presented in Chapter 4. All the design goals have been met. The design exercise has also given insights into possible further improvements. Contributions from this work and course of future development work are indicated in the concluding chapter.

No description available.

The thesis describes theoretical and experimental studies on the chaotic behaviour of a peak current-mode controlled boost converter, a parallel two-module peak current-mode controlled DC-DC boost converter, and a peak current-mode controlled power factor correction (PFC) boost converter. The research concentrates on converters which do not have voltage control loops, since the main interest is in the intrinsic mechanism of chaotic behaviour. These converters produce sub-harmonics of the clock frequency at certain values of the reference current I[ref] and input voltage V[in], and may behave in a chaotic manner, whereby the frequency spectrum of the inductor becomes continuous. Non-linear maps for each of the converters are derived using discrete time modelling and numerical iteration of the maps produce bifurcation diagrams which indicate the presence of subharmonics and chaotic operation. In order to check the validity of the analysis, MATLAB/SIMULINK models for the converters are developed. A comparison is made between waveforms obtained from experimental converters, with those produced by the MATLAB/SIMULINK models of the converters. The experimental and theoretical results are also compared with the bifurcation points predicted by the bifurcation diagrams. The simulated waveforms show excellent agreement, with both the experimental waveforms and the transitions predicted by the bifurcation diagrams. The thesis presents the first application of a delayed feedback control scheme for eliminating chaotic behaviour in both the DC-DC boost converter and the PFC boost converter. Experimental results and FORTRAN simulations show the effectiveness and robustness of the scheme. FORTRAN simulations are found to be in close agreement with experimental results and the bifurcation diagrams. A theoretical comparison is made between the above converters controlled using delayed feedback control and the popular slope compensation method. It is shown that delayed feedback control is a simpler scheme and has a better performance than that for slope compensation.

AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.

AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.