The availability of low-cost wireless devices has enabled wide-scale connectivity over recent years. Today’s wireless devices provide services including voice communication, GPS location, and internet connectivity. With a larger number of supported wireless standards within a single device, new wireless radio techniques are required in order to implement flexible and programmable broadband receivers to replace the standard specific receivers often seen today. The continual growth in the use of the wireless spectrum has led to an increasingly hostile interference environment for such receivers. While interferers may be located out of the signal band of interest, they may still reside within the large band of operation of the broadband receiver, making removal of the interference by filtering difficult. The requirement for small form-factor and cost minimization has made an increased level of integration highly desirable to minimize the number of external filter components required to reject interferers. A key consideration in the design of broadband receivers is the spurious response of the downconversion mixers, where local oscillator (LO) harmonics can lead to downconversion of unfiltered interferers to baseband, along with the desired signal, thus degrading the signal-to-noise ratio. Recent broadband receivers utilize a harmonic rejection mixer to reject LO harmonics within the downconversion mixer and prevent interferers from being downconverted to baseband. This report details the cause of harmonic mixing within CMOS mixers and provides a survey of published circuit techniques robust to device mismatch to remove LO harmonic response. A description of frequency translation and the effect of harmonic mixing on the translation is presented. The theoretical background of the operation of harmonic rejection mixers is described, including the effect of gain and phase errors on the achievable level of harmonic rejection. An overview of published harmonic rejection mixer techniques including the first harmonic rejection mixer and techniques to limit the effects of phase and gain mismatch on harmonic rejection is discussed. The report concludes with the introduction of a novel method for effective synthesis of multiple downconversion local oscillator frequencies within a harmonic rejection mixer. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies. / text

Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems. The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation). High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented. Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers. The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology.