The availability of low-cost wireless devices has enabled wide-scale connectivity over recent years. Today’s wireless devices provide services including voice communication, GPS location, and internet connectivity. With a larger number of supported wireless standards within a single device, new wireless radio techniques are required in order to implement flexible and programmable broadband receivers to replace the standard specific receivers often seen today. The continual growth in the use of the wireless spectrum has led to an increasingly hostile interference environment for such receivers. While interferers may be located out of the signal band of interest, they may still reside within the large band of operation of the broadband receiver, making removal of the interference by filtering difficult. The requirement for small form-factor and cost minimization has made an increased level of integration highly desirable to minimize the number of external filter components required to reject interferers. A key consideration in the design of broadband receivers is the spurious response of the downconversion mixers, where local oscillator (LO) harmonics can lead to downconversion of unfiltered interferers to baseband, along with the desired signal, thus degrading the signal-to-noise ratio. Recent broadband receivers utilize a harmonic rejection mixer to reject LO harmonics within the downconversion mixer and prevent interferers from being downconverted to baseband. This report details the cause of harmonic mixing within CMOS mixers and provides a survey of published circuit techniques robust to device mismatch to remove LO harmonic response. A description of frequency translation and the effect of harmonic mixing on the translation is presented. The theoretical background of the operation of harmonic rejection mixers is described, including the effect of gain and phase errors on the achievable level of harmonic rejection. An overview of published harmonic rejection mixer techniques including the first harmonic rejection mixer and techniques to limit the effects of phase and gain mismatch on harmonic rejection is discussed. The report concludes with the introduction of a novel method for effective synthesis of multiple downconversion local oscillator frequencies within a harmonic rejection mixer. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies. / text

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text