An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2.

No / A coplanar edge-fed triangular patch antenna with an integrated stubline is proposed for harmonic rejection application. The design is aimed to achieve a good impedance matching to 50 ω at the fundamental frequency while suppressing radiation of the first and second harmonics. The antenna is attended to operate around 1GHz, with acceptable power gain above 1dBi and less than -15dBi at the harmonics. Simulated and measured results show a reasonable agreement.

Yes / A novel design strategy for microstrip harmonic-suppression antennas is presented. The computational method is based on an integral equation solver using adaptive surface meshing driven by a genetic algorithm. Two examples are illustrated, all involving design of coaxially-fed air-dielectric patch antennas implanted with shorting and folded walls. The characteristics of the antennas in terms of the impedance responses and far ¯eld radiation patterns are discussed theoretically and experimentally. The performances of all of the GA-optimised antennas were shown to be excellent and the presented examples show the capability of the proposed method in antenna design using GA. / MSCRC

The availability of low-cost wireless devices has enabled wide-scale connectivity over recent years. Today’s wireless devices provide services including voice communication, GPS location, and internet connectivity. With a larger number of supported wireless standards within a single device, new wireless radio techniques are required in order to implement flexible and programmable broadband receivers to replace the standard specific receivers often seen today. The continual growth in the use of the wireless spectrum has led to an increasingly hostile interference environment for such receivers. While interferers may be located out of the signal band of interest, they may still reside within the large band of operation of the broadband receiver, making removal of the interference by filtering difficult. The requirement for small form-factor and cost minimization has made an increased level of integration highly desirable to minimize the number of external filter components required to reject interferers. A key consideration in the design of broadband receivers is the spurious response of the downconversion mixers, where local oscillator (LO) harmonics can lead to downconversion of unfiltered interferers to baseband, along with the desired signal, thus degrading the signal-to-noise ratio. Recent broadband receivers utilize a harmonic rejection mixer to reject LO harmonics within the downconversion mixer and prevent interferers from being downconverted to baseband. This report details the cause of harmonic mixing within CMOS mixers and provides a survey of published circuit techniques robust to device mismatch to remove LO harmonic response. A description of frequency translation and the effect of harmonic mixing on the translation is presented. The theoretical background of the operation of harmonic rejection mixers is described, including the effect of gain and phase errors on the achievable level of harmonic rejection. An overview of published harmonic rejection mixer techniques including the first harmonic rejection mixer and techniques to limit the effects of phase and gain mismatch on harmonic rejection is discussed. The report concludes with the introduction of a novel method for effective synthesis of multiple downconversion local oscillator frequencies within a harmonic rejection mixer. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies. / text

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz.

Yes / Microstrip patch antennas with harmonic suppression are designed and optimised, using a genetic algorithm and applying a novel adaptive meshing program to generate a wire-grid simulation. A coaxially-fed air-dielectric patch antenna design with a folded patch was investigated. It was confirmed that antennas with excellent performances could be designed by this method. / MSCRC

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

Ce travail de thèse entre dans le cadre de projets nationaux et internationaux de radioastronomie d'une manière générale et en particulier dans celui de SKA (Square Kilometre Array). La conception de circuits intégrés d’applications spécifiques devient de plus en plus importante dans ce domaine. La première étape de ce travail consiste à une étude bibliographique sur les inductances actives intégrées et leurs principales applications dédiées à la radioastronomie. Cette étude a permis de faire un état de l'art. Cet état de l'art a fait ressortir que l'intégration de certaines fonctions s'avère particulièrement difficile voire impossible dès lors que l'utilisation d'une inductance est nécessaire. Ceci est essentiellement dû à la taille importante des inductances. Parmi ces fonctions, nous avons le filtrage, certains types de transceivers, le temps de retard, etc. Or ces fonctions sont très importantes dans une architecture de radiofréquence propre aux réseaux d'antennes phasées. Ce travail de thèse est donc consacré à l'étude et la conception de ces différentes fonctions à l'aide des inductances actives basées sur des topologies à gyrateurs en technologie SiGeC 0,25 μm afin de palier aux problèmes d'intégration. Une des finalités de cette thèse est aussi de montrer que la consommation de ce procédé d'intégration n’est pas si excessive pour ces applications, par rapport à l’utilisation d’inductances localisées intégrées occupant une surface importante sur le substrat. Ce dernier point sera un résultat très important pour les projets où la très haute intégration à bas coût est nécessaire, point clé de réussite des réseaux phasés denses du projet international SKA. / This thesis work is part of national and international projects of radio-astronomy in general and in particular that of the SKA (Square Kilometre Array). The design of integrated circuits for specific applications is becoming increasingly important in this field. The first step in this work is a bibliography study on integrated active reactors and their main applications dedicated to radio astronomy. This study allowed making a state of the art. This state of the art has highlighted that the integration of some functions is made especially difficult by the need to use an inductor. This is mainly due to the large size of passive inductors. These functions include the filtering function, some transceivers types, the time delay, etc. But, they are very important in radio-frequency architecture owing to phased array antennas. This thesis propose the study and design of these different functions using active inductors based on gyrators topologies in SiGeC 0.25 μm technology in order to overcome the integration problems. One of the aims of this thesis is to show that the consumption of this integration process is not so excessive for these applications, compared to the use of integrated located inductors occupying a large area on the substrate. This last point is a very important result for projects where high integration at low cost is necessary, key point of the success of dense phased array in the SKA international project.

The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text