The availability of low-cost wireless devices has enabled wide-scale connectivity over recent years. Today’s wireless devices provide services including voice communication, GPS location, and internet connectivity. With a larger number of supported wireless standards within a single device, new wireless radio techniques are required in order to implement flexible and programmable broadband receivers to replace the standard specific receivers often seen today. The continual growth in the use of the wireless spectrum has led to an increasingly hostile interference environment for such receivers. While interferers may be located out of the signal band of interest, they may still reside within the large band of operation of the broadband receiver, making removal of the interference by filtering difficult. The requirement for small form-factor and cost minimization has made an increased level of integration highly desirable to minimize the number of external filter components required to reject interferers. A key consideration in the design of broadband receivers is the spurious response of the downconversion mixers, where local oscillator (LO) harmonics can lead to downconversion of unfiltered interferers to baseband, along with the desired signal, thus degrading the signal-to-noise ratio. Recent broadband receivers utilize a harmonic rejection mixer to reject LO harmonics within the downconversion mixer and prevent interferers from being downconverted to baseband. This report details the cause of harmonic mixing within CMOS mixers and provides a survey of published circuit techniques robust to device mismatch to remove LO harmonic response. A description of frequency translation and the effect of harmonic mixing on the translation is presented. The theoretical background of the operation of harmonic rejection mixers is described, including the effect of gain and phase errors on the achievable level of harmonic rejection. An overview of published harmonic rejection mixer techniques including the first harmonic rejection mixer and techniques to limit the effects of phase and gain mismatch on harmonic rejection is discussed. The report concludes with the introduction of a novel method for effective synthesis of multiple downconversion local oscillator frequencies within a harmonic rejection mixer. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies. / text

The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text