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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Quantum-bit devices inspired by classical stochastic analogies

Washington, Zoe January 2013 (has links)
As systems/structures get smaller we need to take into account noise and quantum effects and so, we need to develop some quantum devices. Quantum devices work using quantum principles like qubits that have already been developed, i.e., superconducting qubits that are going to be discussed in chapter 1. Initially, scientists wanted to use qubits to do quantum computations, this is not easy so scientists developed methods to do something different, e.g. quantum metamaterials. Here in this thesis we describe two examples of quantum devices. Our first device is the parametric quantum amplifier. Used when we need to amplify very weak signals. Amplifying a weak signal on the nanoscale is a very big challenge, this is due to classical and quantum noise, and so, we need to employ quantum physics to resolve this issue. The proposed two-qubit system amplifies weak signals at very small scales. We have shown that we can construct a multitude of novel devices on the nano-scale with the use of qubits Our second device uses harmonic mixing. It can be used where rectification is needed, for example, when we need to rectify some fluctuations and in principle some quantum fluctuations in order to pump either an excited or ground state of the two qubit device. In this thesis we propose how to do this. Firstly, we propose that if we apply harmonic mixing of two signals for two qubits, using the structure of the equation and basically the structure of quantum mechanics we can pump a desirable quantum state. We can pump either the upper or ground state by changing the signal.
2

Circuit techniques for programmable broadband radio receivers

Forbes, Travis Michael, 1986- 02 March 2015 (has links)
The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text

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