A popularização das aplicações que manipulam vídeos digitais de altas resoluções incorpora diversos desafios no desenvolvimento de novas e eficientes técnicas para manter a eficiência na compressão de vídeo. Para lidar com esta demanda, o padrão HEVC foi proposto com o objetivo de duplicar as taxas de compressão quando comparado com padrões predecessores. No entanto, para atingir esta meta, o HEVC impõe um elevado custo computacional e, consequentemente, o aumento no consumo de energia. Este cenário torna-se ainda mais preocupante quando considerados dispositivos móveis alimentados por bateria os quais apresentam restrições computacionais no processamento de aplicações multimídia. A maioria dos trabalhos relacionados com este desafio, tipicamente, concentram suas contribuições no redução e controle do esforço computacional refletido no processo de codificação. Entretanto, a literatura indica uma carência de informações com relação ao consumo de energia despendido pelo processamento da codificação de vídeo e, principalmente, o impacto energético da hierarquia de memória cache neste contexto. Esta tese apresenta uma metodologia para caracterização energética da codificação de vídeo HEVC em processador de propósito geral. O principal objetivo da metodologia proposta nesta tese é fornecer dados quantitativos referentes ao consumo de energia do HEVC. Esta metodologia é composta por dois módulos, um deles voltado para o processamento da codificação HEVC e, o outro, direcionado ao comportamento do padrão HEVC no que diz respeito à memória cache. Uma das principais vantagens deste segundo módulo é manter-se independente de aplicação ou de arquitetura de processador. Neste trabalho, diversas análises foram realizadas visando a caracterização do consumo de energia do codificador HEVC em processador de propósito geral, considerando diferentes sequências de vídeo, resoluções e parâmetros do codificador. Além disso, uma análise extensa e detalhada de diferentes configurações possíveis de memória cache foi realizada com o propósito de avaliar o impacto energético destas configurações na codificação. Os resultados obtidos com a caracterização proposta demonstram que o gerenciamento dos parâmetros da codificação de vídeo, de maneira conjunta com as especificações da memória cache, tem um alto potencial para redução do consumo energético de codificação de vídeo, mantendo bons resultados de qualidade visual das sequências codificadas. / The popularization of high-resolution digital video applications brings several challenges on developing new and efficient techniques to maintain the video compression efficiency. To respond to this demand, the HEVC standard was proposed aiming to duplicate the compression rate when compared to its predecessors. However, to achieve such goal, HEVC imposes a high computational cost and, consequently, energy consumption increase. This scenario becomes even more concerned under battery-powered mobile devices which present computational constraints to process multimedia applications. Most of the related works about encoder realization, typically concentrate their contributions on computational effort reduction and management. Therefore, there is a lack of information regarding energy consumption on video encoders, specially about the energy impact of the cache hierarchy in this context. This thesis presents a methodology for energy characterization of the HEVC video encoder in general purpose processors. The main goal of this methodology is to provide quantitative data regarding the HEVC energy consumption. This methodology is composed of two modules, one focuses on the HEVC processing and the other focuses on the HEVC behavior regarding cache memory-related consumption. One of the main advantages of this second module is to remain independent of application or processor architecture. Several analyzes are performed aiming at the energetic characterization of HEVC coding considering different video sequences, resolutions, and parameters. In addition, an extensive and detailed analysis of different cache configurations is performed in order to evaluate the energy impact of such configurations during the video coding execution. The results obtained with the proposed characterization demonstrate that the management of the video coding parameters in conjunction with the cache specifications has a high potential for reducing the energy consumption of video coding whereas maintaining good coding efficiency results.

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

Over the last years, security-kernels have played a promising role in reshaping the landscape of platform security on embedded devices. Security-kernels, such as separation kernels, enable constructing high-assurance mixed-criticality execution platforms on a small TCB, which enforces isolation between components. The reduced TCB  minimizes the system attack surface and facilitates the use of formal methods to ensure the kernel functional correctness and security. In this thesis, we explore various aspects of building a provably secure separation kernel using virtualization technology. We show how the memory management subsystem can be virtualized to enforce isolation of system components. Virtualization is done using direct-paging that enables a guest software to manage its own memory configuration. We demonstrate the soundness of our approach by verifying that the high-level model of the system fulfills the desired security properties. Through refinement, we then propagate these properties (semi-)automatically to the machine-code of the virtualization mechanism. Further, we show how a runtime monitor can be securely deployed alongside a Linux guest on a hypervisor to prevent code injection attacks targeting Linux. The monitor takes advantage of the provided separation to protect itself and to retain a complete view of the guest. Separating components using a low-level software cannot by itself guarantee the system security. Indeed, current processors architecture involves features that can be utilized to violate the isolation of components. We present a new low-noise attack vector constructed by measuring caches effects which is capable of breaching isolation of components and invalidates the verification of a software that has been verified on a memory coherent model. To restore isolation, we provide several countermeasures and propose a methodology to repair the verification by including data-caches in the statement of the top-level security properties of the system. / <p>QC 20170831</p> / PROSPER / HASPOC

Knowledge of the resource usage of applications and the resource usage capacity of hardware platforms is essential when developing a system. The resource usage must not over exceed the capacity of a platform, as it could otherwise fail to meet its real-time constraints due to resource shortages. Furthermore, it is beneficial from a cost-effectiveness stand-point that a hardware platform is not under-utilised by systems software. This thesis examines two systems aspects: the hardware resource usage of applications and the resource capacity of hardware platforms, defined as the capacity of each resource included in a hardware platform. Both of these systems aspects are investigated and modelled using a black box perspective since the focus is on observing the online usage and capacity. Investigating and modelling these two approaches is a crucial step towards defining and constructing hardware and software models. We evaluate regressive and auto-regressive modelling approaches of modelling CPU, L2 cache and L3 cache usage of applications. The conclusion is that first-order autoregressive and Multivariate Adaptive Regression Splines show promise of being able to model resource usage. The primary limitation of both modelling approaches is their inability to model resource usage when it is highly irregular. The capacity models of CPU, L2 and L3 cache derived by exerting heavy workloads onto a test platform shows to hold against a real-life application concerning L2 and L3 cache capacity. However, the CPU usage model underestimates the test platform's capacity since the real-life application over-exceeds the theoretical maximum usage defined by the model.

Im Rahmen dieser vorliegenden Arbeit soll untersucht werden, welche Möglichkeiten zur Sicherung einer möglichst hohen Verfügbarkeit (High-Availability), Mechanismen zur Lastverteilung mittels des ZEO-Produkts oder ähnlichem sowie welche Strategien des Cachings sinnvoll an einem ZOPE-Server zum Einsatz kommen können. Die Arbeit untersucht dabei die Einsatzmöglichkeiten von bereits vorhandenen und die eventuelle Notwendigkeit der Eigenimplementierung weiterer Produkte der ZOPE-Entwicklung. Den Rahmen der Arbeit bildet die Serverstruktur des Bildungsmarktplatzes Sachsen.

Le rendu de Monte-Carlo par lancer de rayons est connu depuis longtemps pour être une classe d’algorithmes de choix lorsqu’il s’agit de générer des images de synthèse photo-réalistes. Toutefois, sa nature fondamentalement aléatoire induit un bruit caractéristique dans les images produites. Dans cette thèse, nous mettons en œuvre des algorithmes fondés sur les échantillons de Monte-Carlo et l’inférence bayésienne pour factoriser le calcul du rendu, par le partage d’information entre pixels voisins ou la mise en cache de données précédemment calculées. Dans le cadre du rendu à temps long, en nous fondant sur une technique récente de débruitage en traitement d’images, appelée Non-local Bayes, nous avons développé un algorithme de débruitage collaboratif par patchs, baptisé Bayesian Collaborative Denoising. Celui-ci est conçu pour être adapté aux spécificités du bruit des rendus de Monte-Carlo et aux données supplémentaires qu’on peut obtenir par des statistiques sur les échantillons. Dans un deuxième temps, pour factoriser les calculs de rendus de Monte-Carlo en temps interactif dans un contexte de scène dynamique, nous proposons un algorithme de rendu complet fondé sur le path tracing, appelé Dynamic Bayesian Caching. Une partition des pixels permet un regroupement intelligent des échantillons. Ils sont alors en nombre suffisant pour pouvoir calculer des statistiques sur eux. Ces statistiques sont comparées avec celles stockées en cache pour déterminer si elles doivent remplacer ou enrichir les données existantes. Finalement un débruitage bayésien, inspiré des travaux de la première partie, est appliqué pour améliorer la qualité de l’image. / Monte Carlo ray tracing is known to be a particularly well-suited class of algorithms for photorealistic rendering. However, its fundamentally random nature breeds noise in the generated images. In this thesis, we develop new algorithms based on Monte Carlo samples and Bayesian inference in order to factorize rendering computations, by sharing information across pixels or by caching previous results. In the context of offline rendering, we build upon a recent denoising technique from the image processing community, called Non-local Bayes, to develop a new patch-based collaborative denoising algorithm, named Bayesian Collaborative Denoising. It is designed to be adapted to the specificities of Monte Carlo noise, and uses the additionnal input data that we can get by gathering per-pixel sample statistics. In a second step, to factorize computations of interactive Monte Carlo rendering, we propose a new algorithm based on path tracing, called Dynamic Bayesian Caching. A clustering of pixels enables a smart grouping of many samples. Hence we can compute meaningful statistics on them. These statistics are compared with the ones that are stored in a cache to decide whether the former should replace or be merged with the latter. Finally, a Bayesian denoising, inspired from the works of the first part, is applied to enhance image quality.

Due to the short time the updated National School Lunch Program standards have been in place since fall of 2012, few research studies have explored what effect these new standards have had on fruit and vegetable (F/V) consumption, particularly among elementary school students. Because the new standards require schools to offer students more F/V than before, researchers are interested to know if F/V consumption has indeed increased. The participants in the study were enrolled in a program to motivate students to eat more F/V – the Food Dudes program. The results of the data analysis found that most students, regardless of grade, were eating less F/V initially after the new standards were in place. However, the group of students receiving prizes from the Food Dudes program actually ate more F/V over time instead of less. Also, F/V consumption for the first spring under the new standards did not decrease as much as it had during the spring under the old standards. These results indicate that, despite initial declines in F/V consumption, students could be adjusting to the updated standards. Also, students who have participated in the incentives group of the Food Dudes program did not show a drop in F/V consumption, even during the first semester the new standards were in place. Future studies should look at the current F/V intake of students under the updated guidelines now that they have been in place for several school years, as well as at additional intervention programs to increase F/V consumption among this population.

Cette thèse porte sur la construction des algorithmes distribués pour l’optimisation de la production et du partage de ressources au sein d’un réseau de large dimension. Notamment, on se concentre sur les réseaux électriques et les réseaux cellulaires 5G. On considère dans le cas des réseaux électriques le problème OPF (Optimal Power Flow) dans lequel on vise à faire la gestion et l’optimisation de la production de l’énergie électrique d’une manière distribuée. On se concentre sur une version linéarisée du problème, la DC-OPF (Direct-Current Optimal Power Flow). Comme le problème d’optimisation est convexe dans ce cas, on vise à minimiser le coût de production de l’énergie tout en respectant les limites des lignes de transmission et les contraintes caractéristiques du système. Dans le cas des réseaux cellulaires, on formule un problème de Caching. On a pour but de réduire l’utilisation du backhaul liant les stations de base et le contrôleur du réseau. Les stations de base sont équipées d’une capacité de stockage limitée. Ils visent à trouver d’une manière optimale les fichiers à stocker dans le but de réduire une certaine fonction de coût sur l’utilisation du backhaul et sur le partage des fichiers avec les autres stations de base. L’approche adoptée dans cette thèse consiste à appliquer l’ADMM (Alternating Direction Method of Multipliers), une méthode d’optimisation de manière itérative, à un problème d’optimisation que l’on a préalablement reformulée de façon adéquate. Ce problème permet à la fois de décrire le DC-OPF et le problème de Caching. On démontre la convergence de cette méthode quand elle est appliquée noeud par noeudd’une manière totalement distribuée. Ainsi que dans le cas où le réseau est divisé en plusieurs zones. Ces zones peuvent se chevaucher mais aussi elles peuvent être séparées ou indépendantes. De plus, dans le contexte d’un réseau à zones, on démontre que l’application de l’ADMM d’une manière aléatoire par une seule zone converge aussi vers la solution optimale du problème. / This thesis focuses on the construction of distributed algorithms for optimizing resource production in a large interconnected system. In particular, it focuses on power grid and 5G cellular networks. In the case of power grid networks, we consider the OPF (Optimal Power Flow) problem in which one seeks to manage and optimize the production of electrical energy in a distributed manner. We focus on a linearized version of the problem, the DC-OPF (Direct- Current Optimal Power Flow) problem. This optimization problem is convex; the aim is to minimize the cost of energy generation while respecting the limits of the transmission line and the power flow constraints. In the case of 5G cellular networks, we formulate a caching problem. We aim to offload the backhaul link usage connecting the small bases stations (SBSs) to the central scheduler (CS). The SBSs are equipped with a limited storage capacity. We seek to find the optimal way to store files so as to reduce the cost on the use of backhaul and sharing files with other SBSs. The approach adopted in this thesis is to apply the ADMM (Alternating Direction Method of Multipliers), an optimization method that is applied iteratively, to an optimization problem that we adequately formulated previously. This problem can both describe the DC-OPF problem and the Caching problem. We prove the convergence of the method when applied node by node in a fully distributed manner. Additionally, we prove its convergence in the case where the network is divided into multiple areas or nations that may or may not overlap. Furthermore, in the context of a network with multiple areas, we show that the application of ADMM in a random manner by a single randomly chosen area also converges to the optimal solution of the problem.

5G est prévu pour s'attaquer, en plus d'une augmentation considérable du volume de trafic, la tâche de connecter des milliards d'appareils avec des exigences de service hétérogènes. Afin de relever les défis de la 5G, nous préconisons une utilisation plus efficace des informations disponibles, avec plus de sensibilisation par rapport aux services et aux utilisateurs, et une expansion de l'intelligence du RAN. En particulier, nous nous concentrons sur deux activateurs clés de la 5G, à savoir le MIMO massif et la mise en cache proactive. Dans le troisième chapitre, nous nous concentrons sur la problématique de l'acquisition de CSI dans MIMO massif en TDD. Pour ce faire, nous proposons de nouveaux schémas de regroupement spatial tels que, dans chaque groupe, une couverture maximale de la base spatiale du signal avec un chevauchement minimal entre les signatures spatiales des utilisateurs est obtenue. Ce dernier permet d'augmenter la densité de connexion tout en améliorant l'efficacité spectrale. MIMO massif en TDD est également au centre du quatrième chapitre. Dans ce cas, en se basant sur les différents taux de vieillissement des canaux sans fil, la périodicité d'estimation de CSI est supplémentaire. Nous le faisons en proposant un exploité comme un degré de liberté supplémentaire. Nous le faisons en proposant une adaptation dynamique de la trame TDD en fonction des temps de cohérence des canaux hétérogènes. Les stations de bases MIMO massif sont capables d'apprendre la meilleure politique d’estimation sur le uplink pour de longues périodes. Comme les changements de canaux résultent principalement de la mobilité de l'appareil, la connaissance de l'emplacement est également incluse dans le processus d'apprentissage. Le problème de planification qui en a résulté a été modélisé comme un POMDP à deux échelles temporelles et des algorithmes efficaces à faible complexité ont été fournis pour le résoudre. Le cinquième chapitre met l'accent sur la mise en cache proactive. Nous nous concentrons sur l'amélioration de l'efficacité énergétique des réseaux dotes de mise en cache en exploitant la corrélation dans les modèles de trafic en plus de la répartition spatiale des demandes. Nous proposons un cadre qui établit un compromis optimal entre la complexité et la véracité dans la modélisation du comportement des utilisateurs grâce à la classification adaptative basée sur la popularité du contenu. Il simplifie également le problème du placement de contenu, ce qui se traduit par un cadre d'allocation de contenu rapidement adaptable et économe en énergie. / 5G is envisioned to tackle, in addition to a considerable increase in traffic volume, the task of connecting billions of devices with heterogeneous service requirements. In order to address the challenges of 5G, we advocate a more efficient use of the available information, with more service and user awareness, and an expansion of the RAN intelligence. In particular, we focus on two key enablers of 5G, namely massive MIMO and proactive caching. In the third chapter, we focus on addressing the bottleneck of CSI acquisition in TDD Massive MIMO. In order to do so, we propose novel spatial grouping schemes such that, in each group, maximum coverage of the signal’s spatial basis with minimum overlapping between user spatial signatures is achieved. The latter enables to increase connection density while improving spectral efficiency. TDD Massive MIMO is also the focus of the fourth chapter. Therein, based on the different rates of wireless channels aging, CSI estimation periodicity is exploited as an additional DoF. We do so by proposing a dynamic adaptation of the TDD frame based on the heterogeneous channels coherence times. The Massive MIMO BSs are enabled to learn the best uplink training policy for long periods. Since channel changes result primarily from device mobility, location awareness is also included in the learning process. The resulting planning problem was modeled as a two-time scale POMDP and efficient low complexity algorithms were provided to solve it. The fifth chapter focuses on proactive caching. We focus on improving the energy efficiency of cache-enabled networks by exploiting the correlation in traffic patterns in addition to the spatial repartition of requests. We propose a framework that strikes the optimal trade-off between complexity and truthfulness in user behavior modeling through adaptive content popularity-based clustering. It also simplifies the problem of content placement, which results in a rapidly adaptable and energy efficient content allocation framework.