The main objective of the research was the fabrication and characterization of MOS/MIS capacitors with ZnO as the insulating layer. Comparison with the already well known behavior of MOS/MIS capacitors with SiO2 as insulator was used to facilitate determination of the ZnO characteristics. Moreover, thermal annealing of the samples led to increased understanding of the role of defects on the dielectric properties of the ZnO layers in the MOS/MIS devices. Hall-effect transport measurements and x-ray diffraction (XRD) spectroscopy are used to analyze the structure and electronic surface characteristics of the ZnO insulator. Capacitance-voltage (C-V) measurements are used to understand the effect of surface interface charges and fixed oxide charges in the MOS/MIS (metal-oxide (insulator)-semiconductor) capacitor. The results of the Hall-effect measurement will reveal several things; the sheet resistance, carrier concentration, and mobility as well as confirm the type of silicon used. The optical spectrophotometry measurement confirmed the band gap of 3.2 eV for ZnO. The x-ray diffraction data confirmed a (002) orientation polycrystalline wurtzite ZnO structure. Initial capacitance-voltage measurement of SiO2 and ZnO revealed that the capacitance was larger for SiO2 than for ZnO. This study also explores the impact of thermal annealing on the performance of the ZnO capacitors. Hall-effect measurements are used to evaluate the influence of thermal annealing on the resistivity, carrier concentration and mobility as a function of annealing temperature. ZnO is an n-type semiconductor; this n-type conductivity is due to deviations from the stoichiometry as a result of oxygen vacancies and interstitial zinc. After ZnO samples were annealed at different temperatures, the Hall-effect measurements were performed. After thermal annealing, the mobility increased significantly by two orders of magnitude, but both the carrier concentration and the sheet density decreased. A threshold voltage (turn-on) of -1V was observed for the ZnO sample annealed at 980oC. ZnO is very versatile material with the potential for use in field effect transistors, solar cells, sensors, surface acoustic wave devices and photodiodes due to the high conductivity and high transmittance in the visible part of the spectrum. ZnO as an insulator works through analytical solutions, but not necessarily through this investigation. The difference in oxide thickness during rf magentron sputtering change the capacitance for ZnO making it lower. For n-type substrates it appears that the capacitance after annealing was higher than the capacitance before annealing. After annealing, a stretched out capacitance-voltage curve indicates the presence of trapped oxide charges and an unsmoothed surface. A high resistivity material could be used for some devices. However, typically low resistivity materials are used. After ZnO samples were annealed (unetched) at different temperatures, the Hall-effect were performed and the mobility increased significantly by two orders of magnitude, but the sheet density decreased along with the carrier concentration. The only sample that appears to come to a high frequency C-V in equilibrium is the ZnO sample annealed at 980oC. The depletion region was distinguishable and the transition point (threshold voltage) was found to be at -1 V.

There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0–40V) and high voltage (40–5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed. / Master of Science

In this thesis, a novel method of reducing the rear surface recombination in copper indium gallium (di) selenide (CIGS) thin film solar cells, using atomic layer deposited (ALD) Al2O3, has been evaluated via qualitative opto-electrical characterization. The idea stems from the silicon (Si) industry, where rear surface passivation layers are used to boost the open-circuit voltage and, hence, the cell efficiency. To enable a qualitative assessment of the passivation effect, Al/Al2O3/CIGS metal-oxide-semiconductor (MOS) devices with 3-50 nm oxide thickness, some post-deposition treated (i.e. annealed), have been fabricated. Room temperature capacitance-voltage (CV) measurements on the MOS devices indicated a negative fixed charge density (Qf) within the Al2O3 layer, resulting in a reduced CIGS surface recombination due to field effect passivation. After annealing the Al2O3 passivation layers, the field effect passivation appeared to increase due to a more negative Qf. After annealing have also indications of a lower density of interface traps been seen, possibly due to a stronger or activated chemical passivation. Additionally, the feasibility of using ALD Al2O3 to passivate the surface of CIGS absorber layers has also been demonstrated by room temperature photoluminescence (PL) measurements, where the PL intensity was about 20 times stronger for a structure passivated with 25 nm Al2O3 compared to an unpassivated structure. The strong PL intensity for all passivated devices suggests that both the chemical and field effect passivation were active, also for the passivated as-deposited CIGS absorbers.

abstract: As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. The focus of this work is to understand the properties of charges present in the SiNx films and then to develop a mechanism to manipulate the polarity of charges to either negative or positive based on the end-application. Specific silicon-nitrogen dangling bonds (·Si-N), known as K center defects, are the primary charge trapping defects present in the SiNx films. A custom built corona charging tool was used to externally inject positive or negative charges in the SiNx film. Detailed Capacitance-Voltage (C-V) measurements taken on corona charged SiNx samples confirmed the presence of a net positive or negative charge density, as high as +/- 8 x 1012 cm-2, present in the SiNx film. High-energy (~ 4.9 eV) UV radiation was used to control and neutralize the charges in the SiNx films. Electron-Spin-Resonance (ESR) technique was used to detect and quantify the density of neutral K0 defects that are paramagnetically active. The density of the neutral K0 defects increased after UV treatment and decreased after high temperature annealing and charging treatments. Etch-back C-V measurements on SiNx films showed that the K centers are spread throughout the bulk of the SiNx film and not just near the SiNx-Si interface. It was also shown that the negative injected charges in the SiNx film were stable and present even after 1 year under indoor room-temperature conditions. Lastly, a stack of SiO2/SiNx dielectric layers applicable to standard commercial solar cells was developed using a low temperature (< 400 °C) PECVD process. Excellent surface passivation on FZ and CZ Si substrates for both n- and p-type samples was achieved by manipulating and controlling the charge in SiNx films. / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第19185号 / 工博第4062号 / 新制||工||1627(附属図書館) / 32177 / 京都大学大学院工学研究科航空宇宙工学専攻 / (主査)教授 斧 髙一, 教授 木村 健二, 教授 立花 明知 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

We report the experimental observation of hysteresis-free negative capacitance (NC) in thin ferroelectric Hf₀.₅Zr₀.₅O₂ (HZO) films through high-speed pulsed charge-voltage measurements. Hysteretic switching is suppressed by the addition of thin Al₂O₃ layers on top of the HZO to prevent the screening of the polarization. We observe an S-shaped polarization-electric field dependence without hysteresis in agreement with Landau theory, which enables direct extraction of NC modeling parameters for ferroelectric HZO. Hysteresis-free NC is demonstrated down to 100 ns pulse widths limited only by our measurement setup. These results give critical insights into the physics of ferroelectric NC and practical NC device design using ferroelectric HZO.

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In the present work a Metal / organic / inorganic semiconductor hybrid heterostructure (Ag / DiMe−PTCDI / GaAs) was built under UHV conditions and characterised in situ. The aim was to investigate the influence of the organic layer in the surface properties of GaAs(100) and in the electrical response of organic−modified Ag / GaAs Schottky diodes. The device was tested by combining surface−sensitive techniques (Photoemission spectroscopy and NEXAFS) with electrical measurements (current−voltage, capacitance−voltage, impedance and charge transient spectroscopies). Core level examination by PES confirms removal of native oxide layers on sulphur passivated (S−GaAs) and hydrogen plasma treated GaAs(100) (H+GaAs) surfaces. Additional deposition of ultrathin layers of DiMe−PTCDI may lead to a reduction of the surface defects density and thereby to an improvement of the electronic properties of GaAs. The energy level alignment through the heterostructure was deduced by combining UPS and I−V measurements. This allows fitting of the I−V characteristics with electron as majority carriers injected over a barrier by thermionic emission as a primary event. For thin organic layers (below 8 nm thickness) several techniques (UPS, I−V, C−V, QTS and AFM) show non homogeneous layer growth, leading to formation of voids. The coverage of the H+GaAs substrate as a function of the nominal thickness of DiMe−PTCDI was assessed via C−V measurements assuming a voltage independent capacitance of the organic layer. The frequency response of the device was evaluated through C−V and impedance measurements in the range 1 kHz−1 MHz. The almost independent behaviour of the capacitance in the measured frequency range confirmed the assumption of a near geometrical capacitor, which was used for modelling the impedance with an equivalent circuit of seven components. From there it was found a predominance of the space charge region impedance, so that A.C. conduction can only takes place through the parallel conductance, with a significant contribution of the back contact. Additionally a non linear behaviour of the organic layer resistance probably due to the presence of traps was deduced. ( ) ω ' R QTS measurements performed on the heterostructure showed the presence of two relaxations induced by deposition of the organic layer. The first one is attributed to the presence of a deep trap probably located at the metal / organic interface, while the second one has very small activation energy ( ~ 20 meV) which are probably due to disorder at the organic film. Those processes with small activation energies proved to be determinant for fitting the I−V characteristics of DiMe−PTCDI organic modified diodes using the expressions of a trapped charge limited current regime TCLC. Such a model was the best analytical approach found for fitting the I−V response. Further improving probably will involve implementation of numerical calculations or additional considerations in the physics of the device.