This work examines the role of charge redistribution in the self-discharge of electrochemical capacitor electrodes. Electrochemical capacitors are charge storage devices which have high power capability and a long cycle life, but have a low energy density compared to other devices, coupled with a high rate of self-discharge which further diminishes the available energy. The mechanisms of self-discharge in electrochemical capacitors are poorly understood, and it is important to gain a better understanding of the electrode processes which lead to self-discharge, in order to minimize self-discharge and enhance electrochemical capacitor performance. To learn more about charge redistribution and its role in the self-discharge of electrochemical capacitors, multiple self-discharge experiments were performed on carbons with various surface areas/pore structures and in various electrolytes. Charge redistribution was also examined in a model pore (a transmission line circuit based on de Levie?s model of a porous electrode) and results from this model were compared to the self-discharge of a high surface-area carbon. Results demonstrate that charge redistribution is a major component of the self-discharge in high surface-area carbons. Results also indicate that charge redistribution requires a much longer time than previously thought (tens of hours rather than minutes) which further highlights the importance of charge redistribution during self-discharge. Therefore when performing mechanistic studies of self-discharge in electrochemical capacitors, it is important that effects of charge redistribution are not neglected. The self-discharge profiles of various pore shapes were also examined using the model pore, and results emphasize the superiority of cone and cylindrically shaped pores, and the disadvantages of restrictive pore mouths and bottlenecks for high power applications.

<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.</p>

Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.

Une étude théorique couplée à une partie expérimentale a été entreprise sur la dynamique de l'échange de ligand sur des surfaces de nanoclusters (GNC) dans le but de montrer qu'il était possible de contrôler les propriétés structurales et optiques de GNC à travers la composition de la couronne de ligand. Nos études de calcul ont été effectuées par la théorie fonctionnelle de la densité en chimie quantique (approche Kohn - Sham). Nous avons analysé les principales caractéristiques UV - Visible des spectres calculés par TD - DFT / niveau de CAMB3LYP pour les clusters métalliques Au13, Au25 et Au28 protégées par des ligands thiolate, chlorure, et phosphine. Nos résultats montrent qu'il est possible de régler l'énergie de la bande d'absorption la plus basse des clusters d'or par une répartition spécifique des ligands qui contrôle de fait la répartition des charges entre la couronne de ligand et le noyau métallique.En parallèle, nous avons synthétisé une série de clusters de composition Au25 (ATP)x (TP) 18 - x avec 4ATP (4 - aminothiophénol) et TP (thiophénol) par synthèse directe et par échange de ligands. Les mesures de spectroscopie de masse ESI - MS montrent que la nucléarité Au25 est préservée pour tous ces différents clusters. En revanche, l'échange de ligands TP par le DDT (1 - dodécanethiol) dans le mélange conduit à la formation de nanoparticules. Les mesures de spectroscopies IR confirment la présence de deux ligands différents sur la surface de l'or et les analyses SAXS montrent que nous avons une bonne corrélation entre la distance entre deux cœurs métalliques et la longueur du ligand de surface. / We performed a joint computational – experimental investigation of the dynamics of ligand exchange on gold nanoclusters (GNC) surface with the aim to understand how to control the structural and optical properties of GNC through the design of their ligand shell. Our computational studies were carried out in the framework of the Kohn – Sham implementation of density functional theory in quantum chemistry. We analyzed the main features of UV – Vis spectra computed at the TD – DFT / CAMB3LYP level for the Au13, Au25, and Au28 metallic cores protected by thiolate, chloride, and phosphine ligands. Our results show that it is possible to tune the energy of the lowest absorption band of gold clusters by ligand shell engineering in order to control the charge redistribution between ligand shell and metallic core.In parallel we synthesized a set of Au25(ATP)x(TP)18 – x clusters with different ATP/TP ratios using an adapted Demessence protocol by combining 4ATP (4 – aminothiophenol) and TP (thiophenol) ligands. ESI – MS measurements evidence that for these mixed ligand shells the Au25 nuclearity is preserved. However, the addition of the DDT (1 – dodecanethiol) ligand in the mixture leads to nanoparticle formation. FT – IR spectroscopy confirms the absorption of two different ligands on the gold surface and SAXS shows that we have a good correlation between the distance between two clusters and the length of the ligand protecting them.Finally, we carried out a comparison of the mode of binding and the structural and optical properties of the fully ligated PH3 and NHC GNC with metallic cores of different nuclearities.

Práce se zabývá studiem superkondenzátorů (SC). Výstupem je detailní studie principů přenosu náboje ve struktuře SC, ukládání energie a nový náhradní model SC, který je založen na fyzikálních zákonitostech a principech SC. Dále byl vytvořen matematický model SC, který popisuje chování náboje v jeho aktivní vrstvě. SC byly testovány metodami umělého stárnutí. Závislosti poklesu parametrů SC vlivem různých metodik stárnutí jsou v práci shrnuty.

High electron mobility transistors (HEMTs) realized using AlxGa1-xN/GaN are relatively new technology which is prominent for high-speed and high-power applications. Some of the main problems with this technology were identified as dynamic RDSon, current collapse and threshold voltage instabilities due to the off-state stress. What was less investigated is the effect of the off-state stress on the leakage current at lower voltages. In this work, multiple devices with various initial leakage currents are stressed at different stress conditions (drain voltage, temperature, duration) and the development of drain-source on-state resistance (RDSon), threshold voltage (Vth) and drain-source leakage current (IDSS) after stress are tracked. It was found out that devices with initially higher leakage exhibit higher RDSon and Vth before stress, which simulations attributed to the higher Al mole fraction in the back-barrier or less unintentional doping in the channel layer. During the off-state stress (VDS = 900 V), the leakage current shortly rises and then sharply drops, presumably because of the charge redistribution in the back-barrier. After the stress, no larger changes were observed for RDSon and Vth , but they were for the leakage current i.e., initially low leakage devices had post-stress leakage increase, while initially high leakage devices had post-stress leakage decrease. This is assumed to be caused by the charge redistribution. Parasitic capacitance measurements showed the rise of the pre-stress input, output and reverse transfer capacitances with the pre-stress leakage, which could presumably be explained by higher Al mole fraction inducing more charges in the channel layer, deeming higher Al mole fraction in the back-barrier as a main assumed cause for all the observed effects. After the stress, capacitance changes were tentatively explained by the charge redistribution in the back-barrier. Finally, high temperature was shown to significantly reduce the observed long time to recovery. However, more measurements are needed to further observe this influence. Additionally, more experiments (e.g., on wafer, G-ω measurement, etc.) are needed in general to further investigate the mechanisms behind these memory effects. / Transistorer med extra hög elektronmobilitet, sk HEMT-ar (high electron mobility transistor) kan fabriceras med hjälp av materialen galliumnitrid (GaN) och aluminium-galliumnitrid (AlxGa1-xN). GaN HEMT-ar lämpar sig mycket väl för kraftkomponenter för höga frekvenser. Några av problemen med denna nya teknologi är hög resistans mellan ”drain” och ”source”, RDSon, reduktion av mättnadsströmmen (”current collapse”) och instabiliteter hos styrets tröskelspänning (Vth) när komponenterna stressas i avslaget tillstånd. Mindre känt är effekterna av stress för en avslagen komponent på läckströmmen (IDSS) vid låga påkänningar. I detta arbete har komponenter med varierande läckströmmar utsatts för olika typer av stress, t ex drain-spänning och höjd temperatur under olika långa tider samtidigt som parametrarna RDSon, Vth och IDSS har uppmätts. Det kunde noteras att komponenter med initialt högre läckströmmar hade högre RDSon och Vth innan de utsattes för stress, vilket med hjälp av simuleringar kunde visas bero på högre Al-molfraktion i skiktet under AlxGa1-xN-lagret, alternativt lägre dopning i kanal-lagret. Vid stress (VDS = 900 V) med komponenterna i avslaget tillstånd ökade läckströmmen kortvarigt för att sedan minska, troligtvis beroende på att laddningar omfördelas i lagret under kanal-skiktet. Efter stress sågs inte några större förändringar hos RDSon och Vth , men förändringar syntes på läckströmmen: komponenter med initialt låga läckströmmar visade ökning av läckströmmen efter stress, medan komponenter med initialt höga läckströmmar visade en post-stress minskning av läckström. Detta antas bero på den nämnda omfördelningen av laddningar djupare ner i komponenterna. Mätningar av parasitisk kapacitans visade på en ökning av pre-stress in- och ut-kapacitanserna (Ciss, Coss) samt ”gate-drain”-kapacitansen som funktion av pre-stress läckströmmar. Detta kan möjligtvis förklaras av att en högre andel Al inducerar mer laddningar i kanalen, vilket indikerar att högre Al-molfraktion i skiktet under kanal-lagret är orsaken till många av de effekter som setts. Kapacitansförändringar efter stress förklaras troligen av att laddningarna i detta lager återgår. Till sist noteras också att hög temperatur tydligt reducerade den långa tiden som komponenterna behövde för att återhämta sig. Det var också tydligt att mer mätningar är nödvändiga för att ytterligare säkerställa de uppmätta förändringarna, t ex mätningar av G-ω på icke kapslade chips, skulle kunna öka förståelsen för dessa minneseffekter.

Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components. / Tiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja.