No description available.

A method and apparatus are presented for generating suppressed carrier digital clock signals. These clock signals have the advantage of being broad band in nature and thus exhibiting lower power spectral density. Structures or systems utilizing such clock signals would be less likely to create electromagnetic noise of sufficient intensity to interfere with radio frequency systems and services. The apparatus requires only digital logic devices, rather than the analog devices required for frequency- or phase-modulated spread spectrum clock generators. The method provides the opportunity to synchronously demodulate the clock, thus restoring the original narrow band clock signal where required. The apparatus was implemented in a programmable gate array using 20 MHz and 33.33 MHz fundamental clocks. Measurements of the resulting electronic spectra and clock jitter are reported. / Graduation date: 1999

In this dissertation, two important current mode circuit design subjects have been explored. In the first part, the switched-current circuit technique has been investigated. The fundamental performance and limitations of this technique are explored. One of the major limitations, the signal distortion caused by clock feedthrough has been substantially reduced by a newly developed clock feedthrough cancellation technique. In addition, a filter synthesis technique has been developed by directly simulating the structure of digital filter. Several experimental CMOS prototypes have been designed and fabricated. The measured frequency and phase responses demonstrated the feasibility of this synthesis technique. In the second part, a new logic family called current-steering logic has been developed. The fundamental performance and characteristics of this technique have been discussed including the basic inverter and NOR gate with DC analysis, transient analysis and power-delay product. It has been shown that the current-steering logic has, a much smaller current spike than conventional CMOS logic circuits, which is especially desirable in mixed-mode applications. Several experimental prototypes have verified the functionality and performance of this new technique. / Graduation date: 1991

With increasing interest in current-mode analogue processing due to its high performance properties such as speed, bandwidth and accuracy compared to voltage-mode processing, new current-mode alternatives to various conventional circuit designs are appearing. In this report, a novel circuit design to construct a fully-differential current-mode operational amplifier ( OP-AMP ) is suggested. A standard CMOS process and a 5 volt power supply are utilized. Simulation results using SPICE are presented. For the current-amplifier, a highly linear behavior ( THD 0.02% ) and an excellent frequency response ( 10 MHz ) were observed. Using this new differential OP-AMP topology, fully-differential switched-current delay cell and an integrator circuit were also developed successfully. / Graduation date: 1991

Thesis (M.S.)--California Polytechnic State University, 2010. / Mode of access: Internet. Title from PDF title page; viewed on Jan. 21, 2010. Major professor: John Oliver. "Presented to the Electrical Engineering Department faculty of California Polytechnic State University, San Luis Obispo." "In partial fulfillment of the requirements for the Master of Science degree in Electrical Engineering." "January 2010." Includes bibliographical references (p. 119-121).

There has been a constant need for low power techniques to achieve high performance at the lowest possible power dissipation. Lots of works have been done to achieve this target. These works have focused on the different aspects of power reduction. One of these aspects of power saving is Dynamic power reduction. This thesis work is focused on this aspect of power saving by reducing the unnecessary transitioning in the circuit. To achieve this, new method called data gating, is proposed here which stops unnecessary toggling in the circuit using different forms of gating mechanisms. This thesis is organized as follows; first chapter is about the low power design of CMOS circuits. That chapter covers the sources of power dissipation in ICs as well as the techniques that have been used to minimize the power consumption. Second chapter talks more about dynamic power consumption. Techniques used for reducing dynamic power consumption through reduction in switching activities are mentioned in that chapter. Also the new technique, Data Gating, to reduce dynamic power is proposed in second chapter. Third chapter talks about simulation setup, tools used for simulation. Results obtained from different simulations are presented in that chapter. Fourth Chapter is about the analysis of simulation results. It also outlines some possible limitations of the proposed method as well as certain points that need to be considered before applying new technique. Fifth and final chapter summarizes the conclusion and possible future work that can be done to enhance the proposed technique, Data Gating. / text

No description available.

No description available.

No description available.

No description available.