The objective of this thesis is to develop circuit-aware interconnect technology optimization for network-on-chip based many-core architectures. The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of copper. The optimal dimensions thus obtained are used to characterize different network-on-chip topologies based on wiring area utilization, maximum core-to-core channel width, aggregate chip bandwidth and worse case latency. Finally, the advantages of many-core many-tier chips are evaluated for different network-on-chip topologies. Area occupied by a router within a core is shown to be the bottleneck to achieve higher performance in network-on-chip based architectures.

<p>In this report we describe an adaptive simulated annealing method for sizing the devices in analog circuits. The motivation for use an adaptive simulated annealing method for analog circuit design are to increase the efficiency of the design circuit. To demonstrate the functionality and the performance of the approach, an operational transconductance amplifier is simulated. The circuit is modeled with symbolic equations that are derived automatically by a simulator.</p>

This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35[micro]m technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets.

A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e equações que modelam um circuito são compatíveis com a forma desse problema de otimização. Os receptores para sistemas de comunicação modernos realizam o processo de downconvertion usando uma freqüência intermediária baixa ou diretamente em banda-base. As topologias de receptor Zero-IF e Low-IF são preferidas por sua alta capacidade de integração e baixo consumo de área e de potência. Os filtros analógicos são blocos de composição básicos nesses sistemas. Neste trabalho é desenvolvida uma metodologia de projeto baseada na aplicação de programação geométrica para projeto de filtros Gm-C. A metodologia de projeto foi usada para projetar filtros analógicos complexos e reais para os padrões de comunicação Bluetooth e Zigbee IEEE/802.15.4. Os resultados obtidos mostram que a metodologia de projeto proposta neste trabalho é uma solução efetiva para reduzir o tempo de projeto e otimizar o desempenho de filtros analógicos. / The tendency of the microelectronic market is to integrate in the same chip complete electronic systems, including digital, analog and RF circuits simultaneously. The analog part of those systems represents the bottleneck in the design process. The complexity of analog design makes this one an intuitive and creative process but time expensive. An alternative methodology for analog integrated circuits design is to represent the design as a mathematical optimization problem known as geometric programming. The advantages are: global optimum achieved efficiently, and the possibility of design automation. The main disadvantage, is that all the parameters or equations that characterize a circuit are not compatible with the form of this optimization problem. Modern receivers perform downconvertion of the signal using very low, or zero intermediate frequency. Zero-IF and Low-IF topologies are preferred because of their high integration capabilities, and low area and power consumption. Analog filters are basic building blocks of such systems. In this work, a design methodology based on geometric programming is developed, for automated and optimal design of Gm-C filters. The design methodology was used to design analog complex and real filters for the digital communications standards Bluetooth and Zigbee IEEE/802.15.4. The results show that the design methodology proposed in this work is an effective solution for fast, automated and optimal analog filter design

A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e equações que modelam um circuito são compatíveis com a forma desse problema de otimização. Os receptores para sistemas de comunicação modernos realizam o processo de downconvertion usando uma freqüência intermediária baixa ou diretamente em banda-base. As topologias de receptor Zero-IF e Low-IF são preferidas por sua alta capacidade de integração e baixo consumo de área e de potência. Os filtros analógicos são blocos de composição básicos nesses sistemas. Neste trabalho é desenvolvida uma metodologia de projeto baseada na aplicação de programação geométrica para projeto de filtros Gm-C. A metodologia de projeto foi usada para projetar filtros analógicos complexos e reais para os padrões de comunicação Bluetooth e Zigbee IEEE/802.15.4. Os resultados obtidos mostram que a metodologia de projeto proposta neste trabalho é uma solução efetiva para reduzir o tempo de projeto e otimizar o desempenho de filtros analógicos. / The tendency of the microelectronic market is to integrate in the same chip complete electronic systems, including digital, analog and RF circuits simultaneously. The analog part of those systems represents the bottleneck in the design process. The complexity of analog design makes this one an intuitive and creative process but time expensive. An alternative methodology for analog integrated circuits design is to represent the design as a mathematical optimization problem known as geometric programming. The advantages are: global optimum achieved efficiently, and the possibility of design automation. The main disadvantage, is that all the parameters or equations that characterize a circuit are not compatible with the form of this optimization problem. Modern receivers perform downconvertion of the signal using very low, or zero intermediate frequency. Zero-IF and Low-IF topologies are preferred because of their high integration capabilities, and low area and power consumption. Analog filters are basic building blocks of such systems. In this work, a design methodology based on geometric programming is developed, for automated and optimal design of Gm-C filters. The design methodology was used to design analog complex and real filters for the digital communications standards Bluetooth and Zigbee IEEE/802.15.4. The results show that the design methodology proposed in this work is an effective solution for fast, automated and optimal analog filter design

This study described an alternative approach for flotation circuit optimization using a mathematical programming technique. Mathematical formulation resulted in mixed integer nonlinear programming problem. Experimental method was used to determine operating conditions of flotation circuit such as flotation circuit stream grades. These conditions were used as the basis for solving optimization problem formulated. The results of the optimization problem were obtaining by setting up the problem in MATLAB optimization toolbox. Performance of flotation circuit in terms of recovery with respect to operating conditions such as residence, number of cells and rate constant has been presented. Stage recoveries were presented as well as overall recovery of the entire flotation circuit. Optimization strategy used superstructure to compare and analyse different alternatives flotation circuits configurations on the basis of stage recoveries. Five circuit alternatives were evaluated are best performing were identified. The statistical analysis was carried out using Statistical Package for Social Sciences (SPSS) software for analysing data derived from mathematical formulation developed for three stages of flotation circuit. Statistically, alternatives A and B can be considered as the most efficient alternatives for the Rougher recovery since they have the same highest means relative to others. Alternative B has the highest mean of 0.995 followed by Alternative A with a mean of 0.991, the least being alternatives D, C and E, respectively. These results imply that Alternative B could be the most efficient alternatives for overall circuit recovery against all other alternatives. One of the key findings were that recovery rate at the rougher stage is higher than the one at the cleaner stage. This results also showed flotation circuits with recycle streams yield comparatively good performance in terms of recovery at rougher stage as compared to circuit without recycle stream. / Civil and Chemical Engineering / M. Tech. (Chemical Engineering)

Submitted by Aline Batista (alinehb.ufpel@gmail.com) on 2017-03-23T21:50:38Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Têmpera simulada aplicada no mapeamento tecnológico de FPGAs baseadas em LUTs.pdf: 6180241 bytes, checksum: 0999141a1ddfa162736db78d94e29dee (MD5) / Approved for entry into archive by Aline Batista (alinehb.ufpel@gmail.com) on 2017-03-28T20:27:26Z (GMT) No. of bitstreams: 2 Têmpera simulada aplicada no mapeamento tecnológico de FPGAs baseadas em LUTs.pdf: 6180241 bytes, checksum: 0999141a1ddfa162736db78d94e29dee (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) / Made available in DSpace on 2017-04-05T19:12:51Z (GMT). No. of bitstreams: 2 Têmpera simulada aplicada no mapeamento tecnológico de FPGAs baseadas em LUTs.pdf: 6180241 bytes, checksum: 0999141a1ddfa162736db78d94e29dee (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Previous issue date: 2015-05-19 / Existem várias técnicas para a otimização de atributos de circuitos integrados. O foco atual dessas técnicas é a minimização da área do circuito em questão. Porém, as técnicas existentes possuem diversas etapas que precisam ser melhoradas, entre elas a etapa de Mapeamento Tecnológico (MT). O Mapeamento Tecnológico é uma etapa crucial no processo de síntese lógica, pois ele define qual conjunto de elementos lógicos serão utilizados para implementar o circuito na tecnologia alvo. Na literatura existem várias abordagens diferentes para otimização da etapa de mapeamento e atualmente as metodologias iterativas estão se popularizado. Esta dissertação propõe uma nova abordagem para o Mapeamento Tecnológico de Field Programmable Gate Arrays (FPGAs), baseada em técnicas de otimização de Inteligência Artificial (IA), mais especificamente a técnica de Têmpera Simulada. A utilização de uma técnica de IA no Mapeamento Tecnológico é uma abordagem promissora pois se diferencia fortemente das técnicas já existentes, devido aos fatores de aleatoriedade em técnicas de otimização baseados em IA. A abordagem elaborada age em uma etapa do mapeamento chamada de cobertura, criando uma solução para o circuito baseada no número de cortes-K necessários para uma cobertura total do mesmo. Cada corte-K pode ser diretamente relacionado a uma Look-Up Table(LUT) da tecnologia FPGA, permitindo assim a geração de um circuito com a lógica equivalente a requisitada. Essa abordagem foi implementada na ferramenta FlexMap, a qual é um framework para o desenvolvimento de métodos para o MT. Foram realizados testes em 85 benchmarks dos pacotes ISCAS85 e MCNC91, amplamente conhecidos na área e frequentemente utilizados para testes de desempenho de novas abordagens. Os testes realizados apresentaram resultados promissores, mostrando que a abordagem desenvolvida consegue encontrar soluções comparáveis em vários casos a ferramenta ABC, considerada estado-da-arte no processo de MT. Os resultados obtidos pela abordagem proposta obtiveram melhoras em aproximadamente 19% dos casos avaliados com K=4 e 26% dos casos com K=5 sobre os resultados do ABC. / Currently there are several techniques for integrated circuit’s atribute optimization. The current focus of these techniques is to minimize the area of the given circuit. These current techniques, however, have several stages that need improvement, including the Technology Mapping stage. The technology mapping is a crucial step in the logic synthesis process, because it de?nes which set of logic elements will be used to implement the circuit in the target technology. In the literature there are several different approaches to optimize the mapping stage and currently iterative methodologies are becoming popular. This dissertation proposes a new approach to Technology Mapping of Field Programmable Gate Arrays (FPGAs), based on optimization techniques using Arti?cial Intelligence (AI), more speci?cally the Simulated Annealing technique, in order to propose an alternative solution to the problem. The utilization of an AI technique in technology mapping is promissing approach because it strongly differs from existing techniques due to the randomness factors in optimization techniques based on AI. The developed approach acts on the mapping stage called coverage, creating a solution for the circuit based on the number of k-cuts needed for a complete coverage. Each k-cut can be directly related to a FPGA’s Look-Up Table (LUT), allowing the generation of a circuit equivalent to the required logic. This approach has been implemented in the FlexMap tool, which is a framework for developing Technology Mapping methods. Tests were performed in 85 benchmarks of the ISCAS85 and MCNC91 packages, widely known in the area and commonly used for performance testing of new approaches. The tests conducted in the implemented approach had promising results, showing that the developed technique can ?nd solutions comparable in several cases to the ABC tool, which is considered state-of-the-art in the Technology Mapping process. The results obtained by the proposed approach obtained improvements in approximately 19% of the evaluated benchmarks with K=4 and 26% with K=5 over ABC’s results.

Conventional hydraulic brake (CHB) systems used in automotive industry have several limitations and disadvantages such as the response delay, wear of braking pad, requirement for auxiliary components (e.g. hydraulic pump, transfer pipes and brake fluid reservoir) and increased overall weight due to the auxiliary components. In this thesis, the development of a novel electromechanical brake (EMB) for automotive applications is presented. Such brake employs mechanical components as well as electrical components, resulting in more reliable and faster braking actuation. The proposed electromagnetic brake is a magnetorheological (MR) brake. The MR brake consists of multiple rotating disks immersed into an MR fluid and an enclosed electromagnet. When current is applied to the electromagnet coil, the MR fluid solidifies as its yield stress varies as a function of the magnetic field applied by the electromagnet. This controllable yield stress produces shear friction on the rotating disks, generating the braking torque. This type of braking system has the following advantages: faster response, easy implementation of a new controller or existing controllers (e.g. ABS, VSC, EPB, etc.), less maintenance requirements since there is no material wear and lighter overall weight since it does not require the auxiliary components used in CHBs. The MRB design process included several critical design steps such as the magnetic circuit design and material selection as well as other practical considerations such as cooling and sealing. A basic MRB configuration was selected among possible candidates and a detailed design was obtained according to a set of design criteria. Then, with the help of a finite element model (FEM) of the MRB design, the magnetic field intensity distribution within the brake was simulated and the results were used to calculate the braking torque generation. In order to obtain an optimal MRB design with higher braking torque generation capacity and lower weight, the key design parameters were optimized. The optimization procedure also consisted of the FEM, which was required to calculate the braking torque generation in each iteration. Two different optimization search methods were used in obtaining the minimum weight and maximum braking torque: (i) a random search algorithm, simulated annealing, was first used to find an approximate optimum design and (ii) a gradient based algorithm, sequential quadratic programming, was subsequently used to obtain the optimum dimensional design parameters. Next, the optimum MRB was prototyped. The braking performance of the prototype was tested and verified, and the experimental results were shown. Also, experimental results were compared with the simulation results. Due to the lack of accurate material property data used in the simulations, there were discrepancies between the experimental and the simulation results. Other possible sources of errors are also discussed. Since the prototype MRB generates much lower braking torque compared to that of a similar size CHB, possible design improvements are suggested ton further increase the braking torque capacity. These include the relaxation of the optimization constraints, introduction of additional disks, and the change in the basic magnetic circuit configuration.

This master’s thesis first deals with the theory concerning induction motor. It briefly desbribes the construction of three-phase induction motors, the generation of tractive force, power flow with loss distribution and also torque characteristic. In the next part an analytical calculation of the parameters of equivalent circuit for an existing induction motor with known dimensions is performed. After the calculation it is possible to find out the rated parameters of the motor, which makes it possible to further compare results with the values obtained by other methods. The next step was to create a model of the motor in RMxprt program, which is later also translated to ANSYS Maxwell 2D model. Simulations were carried out in both interfaces. As the next step the results obtained by the three methods are compared with measured values and also evaluated. The final part of the thesis focuses on the optimization of the magnetic circuit for higher frequencies. Efficiency of the modified induction motor is examined for higher frequencies using RMxprt Optimetrics and this procedure is performed for both default and alternative electrical steel materials.

In recent years, there has been a strong need for the design of integrated  circuits showing low power consumption. It is possible to create intentionally approximate circuits which don't fully implement the specified logic behaviour, but exhibit improvements in term of area, delay and power consumption. These circuits can be used in many error resilient applications, especially in signal and image processing, computer graphics, computer vision and machine learning. This work describes an evolutionary approach to approximate design of arithmetic circuits and other more complex systems. This text presents a parallel calculation of a fitness function. The proposed method accelerated evaluation of 8-bit approximate multiplier 170 times in comparison with the common version. Evolved approximate circuits were used in different types of edge detectors.