The Free Electron Laser (FEL) and Rail Gun are electric weapons which will require a significant amount of stored energy for operation. These types of weapons are ideal for use onboard an all-electric ship. An investigation is made of the effects these weapons will have on a proposed electrical system architecture using simulation modeling. Specifically, this thesis identifies possible design weaknesses and shows where further research and modeling is needed in order to ensure the proper integration of these electric weapons onboard an all-electric ship. The integration of these electric weapon systems with the power systems on electric ships will have an impact on naval operations. Several scenarios concerning specific naval missions are investigated using simulation software to understand the impact and limitations on the electric system using these new electric weapons.

by Ma Hon-chung. / Bibliography: leaves [199]-[204] / Thesis (M.Ph.)--Chinese University of Hong Kong, 1984

Tse Tin-wah. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1988. / Bibliography: leaves [73]-[78]

Bibliography: leaves 136-153. Investigates techniques to achieve performance improvement in Very Long Instruction Word machines through predicated execution.

This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a Simultaneous Multithreading (SMT) architecture. First, the hybrid multithreaded execution model is discussed. This model combines software-controlled multithreading with hardware support for efficient context switching and thread scheduling. A thread scheduling technique called set scheduling is introduced and its impact on the overall performance is described. An analytical model of the hybrid multithreaded execution is developed and validated by simulation. Through stochastic simulation, we find that the application of the hybrid multithreaded execution model results in higher processor utilization than traditional software-controlled multithreading. Next, in the main part of this dissertation, a new architecture is proposed: the Dynamic Simultaneous Multithreading (DSMT) processor. In this architecture, multiple threads are identified and created speculatively at runtime without compiler help. Subsequently, a SMT processor core executes those threads. The performance of a DSMT processor was evaluated with a new execution-driven simulator developed specifically for the purpose. Our experimental results based on simulation show that DSMT architecture has very good potential to improve SMT processor's performance when there is only a single task available for execution. / Graduation date: 2003

Thesis (M.S.)--Oregon Graduate Center, 1984.

Thesis (Ph. D.)--University of Washington, 1982. / Vita. Includes bibliographical references.

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.

Thesis (Ph. D.)--Auburn University, 2008. / Abstract. Includes bibliographical references (p. 127-134).