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Analysis and improvement of performance and power consumption of chip multi-threading SMP architecturesGrant, Ryan Eric 28 August 2007 (has links)
Emerging processor technologies are becoming commercially available that make multi-processor capabilities affordable for use in a large number of computer systems. Increasing power consumption by this next generation of processors is a growing concern as the cost of operating such systems continues to increase.
It is important to understand the characteristics of these emerging technologies in order to enhance their performance. By understanding the characteristics of high performance computing workloads on real systems, the overall efficiency with which such workloads are executed can be increased. In addition, it is important to determine the best trade-off between system performance and power consumption using the variety of system configurations that are possible with these new technologies.
This thesis seeks to provide a comprehensive presentation of the performance characteristics of several real commercially available simultaneous-multithreading multi-processor architectures and provide recommendations to improve overall system performance. As well, it will provide solutions to reduce the power consumption of such systems while minimizing the performance impact of these techniques on the system.
The results of the research conducted show that the new scheduler proposed in this thesis is capable of providing significant increases in efficiency for traditional and emerging multi-processor technologies. These findings are confirmed using real system performance and power measurements. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-08-16 16:06:15.414
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An architecture for reliable decentralized systemsAllchin, James Edward January 1983 (has links)
No description available.
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Active networks : architectures, composition, and applicationsBhattacharjee, Samrat January 1999 (has links)
No description available.
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Architecture mechanics for software directed management of coherent cachesShah, Gautam H. January 1996 (has links)
No description available.
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The design and performance of a parallel computer architecture for simulationHamblen, James Ovid 05 1900 (has links)
No description available.
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ILP-SIMD : an instruction parallel SIMD architecture with short-wire interconnectsChung, Kee Shik 05 1900 (has links)
No description available.
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Constructing adaptable and scalable synthetic benchmarks for microprocessor performance evaluationJoshi, Ajay Manohar, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.
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Designs for a cortically-inspired neurocomputer architecture /Means, Eric, January 1991 (has links)
Thesis (M.S.)--Oregon Graduate Institute of Science and Technology, 1991.
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A merit-based architecture for the automatic selection and composition of services in soa-based C4ISR systemsCook, Thomas S. January 2008 (has links) (PDF)
Thesis (Ph.D. in Software Engineering)--Naval Postgraduate School, June 2008. / Thesis Advisor(s): Michael, James B. "June 2008." Description based on title screen as viewed on August 25, 2008. Includes bibliographical references (p. 155-158). Also available in print.
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Architectures for floating-point divisionNikmehr, Hooman. January 2005 (has links)
Thesis (Ph.D.) --University of Adelaide, School of Electrical and Electronic Engineering, 2005. / Bibliography: pages 241-258. Also available in print form.
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