Global ETD Search

391	Methods for 3D Structured Light Sensor Calibration and GPU Accelerated Colormap Kurella, Venu January 2018 (has links) In manufacturing, metrological inspection is a time-consuming process. The higher the required precision in inspection, the longer the inspection time. This is due to both slow devices that collect measurement data and slow computational methods that process the data. The goal of this work is to propose methods to speed up some of these processes. Conventional measurement devices like Coordinate Measuring Machines (CMMs) have high precision but low measurement speed while new digitizer technologies have high speed but low precision. Using these devices in synergy gives a significant improvement in the measurement speed without loss of precision. The method of synergistic integration of an advanced digitizer with a CMM is discussed. Computational aspects of the inspection process are addressed next. Once a part is measured, measurement data is compared against its model to check for tolerances. This comparison is a time-consuming process on conventional CPUs. We developed and benchmarked some GPU accelerations. Finally, naive data fitting methods can produce misleading results in cases with non-uniform data. Weighted total least-squares methods can compensate for non-uniformity. We show how they can be accelerated with GPUs, using plane fitting as an example. / Thesis / Doctor of Philosophy (PhD) GPU acceleration 3D Structured Light Sensor CMM 3D sensor calibration GPGPU Coordinate Measuring Machines Accelerated colormap Weighted total least squares CUDA Blue LED sensor Point cloud to CAD Snapshot sensor Angled calibration artefact Synergistic hybrid sensor Graphics Processing Unit
392	ML implementation for analyzing and estimating product prices / ML implementation för analys och estimation av produktpriser Kenea, Abel Getachew, Fagerslett, Gabriel January 2024 (has links) Efficient price management is crucial for companies with many different products to keep track of, leading to the common practice of price logging. Today, these prices are often adjusted manually, but setting prices manually can be labor-intensive and prone to human error. This project aims to use machine learning to assist in the pricing of products by estimating the prices to be inserted. Multiple machine learning models have been tested, and an artificial neural network has been implemented for estimating prices effectively. Through additional experimentation, the design of the network was fine-tuned to make it compatible with the project’s needs. The libraries used for implementing and managing the machine learning models are mainly ScikitLearn and TensorFlow. As a result, the trained model has been saved into a file and integrated with an API for accessibility. Machine Learning ML Regression Deep Learning Artificial Neural Network ANN TensorFlow ScikitLearn CUDA cuDNN Estimation Prediction AI Artificial Intelligence Price Tracking Price Logging Price Estimation Supervised Learning Random Forest Decision Trees Batch Learning Hyperparameter Tuning Linear Regression Multiple Linear Regression Maskininlärning Djup lärning Artificiellt Neuralt Nätverk Regression TensorFlow SciktLearn ML ANN Estimation Uppskattning CUDA cuDNN AI Artificiell Intelligens pris loggning pris estimation prisspårning Batchinlärning Hyperparameterjustering Linjär Regression Multipel Linjär Regression Supervised Learning Random Forest Decision Trees Computer Engineering Datorteknik
393	Modeling and Analysis of Large-Scale On-Chip Interconnects Feng, Zhuo 2009 December 1900 (has links) As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high dimensional process-voltage-temperature (PVT) variations demand much more modeling and analysis efforts than ever before, while the analysis of large scale on-chip interconnects that requires solving tens of millions of unknowns imposes great challenges in computer aided design areas. This dissertation presents new methodologies for addressing the above two important challenging issues for large scale on-chip interconnect modeling and analysis: In the past, the standard statistical circuit modeling techniques usually employ principal component analysis (PCA) and its variants to reduce the parameter dimensionality. Although widely adopted, these techniques can be very limited since parameter dimension reduction is achieved by merely considering the statistical distributions of the controlling parameters but neglecting the important correspondence between these parameters and the circuit performances (responses) under modeling. This dissertation presents a variety of performance-oriented parameter dimension reduction methods that can lead to more than one order of magnitude parameter reduction for a variety of VLSI circuit modeling and analysis problems. The sheer size of present day power/ground distribution networks makes their analysis and verification tasks extremely runtime and memory inefficient, and at the same time, limits the extent to which these networks can be optimized. Given today?s commodity graphics processing units (GPUs) that can deliver more than 500 GFlops (Flops: floating point operations per second). computing power and 100GB/s memory bandwidth, which are more than 10X greater than offered by modern day general-purpose quad-core microprocessors, it is very desirable to convert the impressive GPU computing power to usable design automation tools for VLSI verification. In this dissertation, for the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with very promising performance. Our GPU based network analyzer is capable of solving tens of millions of power grid nodes in just a few seconds. Additionally, with the above GPU based simulation framework, more challenging three-dimensional full-chip thermal analysis can be solved in a much more efficient way than ever before.
394	Amélioration des performances de méthodes Galerkin discontinues d'ordre élevé pour la résolution numérique des équations de Maxwell instationnaires sur des maillages simplexes Charles, Joseph 26 April 2012 (has links) (PDF) Cette étude concerne le développement d'une méthode Galerkin discontinue d'ordre élevé en domaine temporel (DGTD), flexible et efficace, pour la résolution des équations de Maxwell instationnaires sur des maillages simplexes destructurés et reposant sur des schémas d'intégration en temps explicites. Les composantes du champ électromagnétique sont approximées localement par des méthodes d'interpolation polynomiale et la continuité entre éléments adjacents est renforcée de façon faible par un schéma centré pour le calcul du flux numérique à travers les interfaces du maillage. L'objectif de cette thèse est de remplir deux objectifs complémentaires. D'une part, améliorer la flexibilité de l'approximation polynomiale en vue du développement de méthodes DGTD p-adaptatives par l'étude de différentes méthodes d'interpolation polynomiale. Plusieurs aspects tels que la nature nodale ou modale de l'ensemble des fonctions de bases associées, leur éventuelle structure hiérarchique, le conditionnement des matrices élémentaires à inverser, les propriétés spectrales de l'interpolation ou la simplicité de programmation sont étudiés. D'autre part, augmenter l'efficacité de l'approximation temporelle sur des maillages localement raffinés en utilisant une stratégie de pas de temps local. Nous développerons finalement dans cette étude une méthodologie de calcul haute performance pour exploiter la localité et le parallélisme inhérents aux méthodes DGTD combinés aux capacités de calcul sur carte graphique. La combinaison de ces caractéristiques modernes résulte en une amélioration importante de l'efficacité et en une réduction significative du temps de calcul. Electromagnétisme Equations de Maxwell en domaine temporel Méthode Galerkin discontinue Méthodes de type hp Interpolation polynomiale Maillage localement raffiné Calcul haute performance Processeurs graphiques (GPU) CUDA Stabilité Convergence Précision d'ordre élevé
395	Integer Factorization on the GPU / Integer Factorization on the GPU Podhorský, Jiří January 2014 (has links) This work deals with factorization, a decomposition of composite numbers on prime numbers and possibilities of its parallelization. It summarizes also the best known algorithms for factoring and most popular platforms for the implementation of these algorithms on the graphics card. The main part of the thesis deals with the design and implementation of hardware acceleration current fastest algorithm on the graphics card by using the OpenCL framework. Subsequently, the work provides a comparison of speeds accelerated algorithm implemented in this work with other versions of the best known algorithms for factoring, processed serially. In conclusion, the work discussed length of RSA key needed for safe operation without the possibility of breaking in real time interval.
396	Zobrazování medicínských dat v reálném čase / Medical Data Rendering in Real-Time Lengyel, Kristián January 2010 (has links) This thesis deals with design and implementation of an application for medical data imaging in real-time. The first part of project is focused on methods for obtaining data in medical practice and visualization of large volume data on computer using familiar rendering approaches. Similar applications are used outside of medicine in other fields, such as chemistry to display molecular structures or microorganisms. Another part of project will focus on benefits of visualization of volumetric data using programmable hardware and new methods of parallelization of algorithms on graphics card using CUDA technology, and OpenCL. The resulting application will display the volume of medical data based on selected method accelerated by programmable shaders, and time-consuming operations will be paralleled on graphics card.
397	Detekce pohyblivého objektu ve videu na CUDA / Moving Object Detection in Video Using CUDA Čermák, Michal January 2011 (has links) This thesis deals with model-based approach to 3D tracking from monocular video. The 3D model pose dynamically estimated through minimization of objective function by particle filter. Objective function is based on rendered scene to real video similarity.
398	Parallel acceleration of deadlock detection and avoidance algorithms on GPUs Abell, Stephen W. 08 1900 (has links) Indiana University-Purdue University Indianapolis (IUPUI) / Current mainstream computing systems have become increasingly complex. Most of which have Central Processing Units (CPUs) that invoke multiple threads for their computing tasks. The growing issue with these systems is resource contention and with resource contention comes the risk of encountering a deadlock status in the system. Various software and hardware approaches exist that implement deadlock detection/avoidance techniques; however, they lack either the speed or problem size capability needed for real-time systems. The research conducted for this thesis aims to resolve issues present in past approaches by converging the two platforms (software and hardware) by means of the Graphics Processing Unit (GPU). Presented in this thesis are two GPU-based deadlock detection algorithms and one GPU-based deadlock avoidance algorithm. These GPU-based algorithms are: (i) GPU-OSDDA: A GPU-based Single Unit Resource Deadlock Detection Algorithm, (ii) GPU-LMDDA: A GPU-based Multi-Unit Resource Deadlock Detection Algorithm, and (iii) GPU-PBA: A GPU-based Deadlock Avoidance Algorithm. Both GPU-OSDDA and GPU-LMDDA utilize the Resource Allocation Graph (RAG) to represent resource allocation status in the system. However, the RAG is represented using integer-length bit-vectors. The advantages brought forth by this approach are plenty: (i) less memory required for algorithm matrices, (ii) 32 computations performed per instruction (in most cases), and (iii) allows our algorithms to handle large numbers of processes and resources. The deadlock detection algorithms also require minimal interaction with the CPU by implementing matrix storage and algorithm computations on the GPU, thus providing an interactive service type of behavior. As a result of this approach, both algorithms were able to achieve speedups over two orders of magnitude higher than their serial CPU implementations (3.17-317.42x for GPU-OSDDA and 37.17-812.50x for GPU-LMDDA). Lastly, GPU-PBA is the first parallel deadlock avoidance algorithm implemented on the GPU. While it does not achieve two orders of magnitude speedup over its CPU implementation, it does provide a platform for future deadlock avoidance research for the GPU. Deadlock Detection Resource Allocation Graph (RAG) GPU CUDA Bit Vector Graphics processing units -- Programming Image processing -- Digital techniques Computer graphics Operating systems (Computers) Engineering graphics Computer software -- Testing Vector analysis Real-time programming -- Research Computer algorithms -- Research
399	Akcelerace genetického algoritmu s využitím GPU / The GPU-Based Acceleration of the Genetic Algorithm Pospíchal, Petr January 2009 (has links) This thesis represents master's thesis focused on acceleration of Genetic algorithms using GPU. First chapter deeply analyses Genetic algorithms and corresponding topics like population, chromosome, crossover, mutation and selection. Next part of the thesis shows GPU abilities for unified computing using both DirectX/OpenGL with Cg and specialized GPGPU libraries like CUDA. The fourth chapter focuses on design of GPU implementation using CUDA, coarse-grained and fine-grained GAs are discussed, and completed by sorting and random number generation task accelerated by GPU. Next chapter covers implementation details -- migration, crossover and selection schemes mapped on CUDA software model. All GA elements and quality of GPU results are described in the last chapter.
400	CUDA-based Scientific Computing / Tools and Selected Applications Kramer, Stephan Christoph 22 November 2012 (has links) No description available. 510 CUDA C++ Expression Templates Preconditioning Sparse Matrix Indoor Airflow Quantum Hall Effect Magnetic Focussing Hardy Space Infinite Elements Phase Retrieval Optogenetics Object-oriented Design FFT Dielectric Relaxation Spectroscopy Poisson-Nernst-Planck Equations BEM FEM-BEM Coupling Curvilinear Boundaries Boundary Integral Equation Transparent Boundary Conditions Schrödinger Equation Krylov Methods Parallel Computing GPU Computing Sparse Approximate Inverse Faber Polynomials Polynomial Preconditioner Conformational Sampling of Proteins Protein Folding Higher Order Finite Elements Mathematics (PPN61756535X)

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