In this thesis, a post-processing deblocking filter is proposed to reduce the blocking effects. This proposed algorithm is suitable for the current block-based video standards without any modification. The proposed algorithm uses Sobel operator and wavelet transform to accurately detect blocking effects at 4¡Ñ4 or 8¡Ñ8 blocking boundaries automatically. In the filtering stage, the proposed algorithm provides four filter modes to eliminate blocking effects at different color regions according to human color vision and color psychology analysis. Experimental results show that the proposed algorithm has better subjective and objective qualities for H.264/AVC reconstructed video sequences compared with several existing methods.

H.264/MPEG-4 part 10 or Advanced Video Coding (AVC) is a standard for video compression. MPEG-4 is currently one of the most widely used formats for recording, compression and distribution of high definition video. One feature of the AVC codec is the inclusion of an in-loop deblocking filter. The goal of the deblocking filter is to remove blocking artifacts that exist at macroblock boundaries. However, due to the complexity of the deblocking algorithm, the filter can easily account for one-third of the computational complexity of a decoder. In this thesis, a modification to the deblocking algorithm given in the AVC standard is presented. This modification allows the algorithm to finish the filtering of a macroblock to finish twenty clock cycles faster than previous single filter designs. This thesis also presents a hardware architecture of the H.264 deblocking filter to be used in the H.264 decoder. The developed architecture allows the filtering of videos streams using 4:2:2 chroma subsampling and 10-bit pixel precision in real-time. The filter was described in VHDL and synthesized for a Spartan-6 FPGA device. Timing analysis showed that is was capable of filtering a macroblock using 4:2:0 chroma subsampling in 124 clock cycles and 4:2:2 chroma subsampling streams in 162 clock cycles. The filter can also provide real-time deblocking of HDTV video (1920x1080) of up to 988 frames per second.

H.264/MPEG-4 part 10 or Advanced Video Coding (AVC) is a standard for video compression. MPEG-4 is currently one of the most widely used formats for recording, compression and distribution of high definition video. One feature of the AVC codec is the inclusion of an in-loop deblocking filter. The goal of the deblocking filter is to remove blocking artifacts that exist at macroblock boundaries. However, due to the complexity of the deblocking algorithm, the filter can easily account for one-third of the computational complexity of a decoder. In this thesis, a modification to the deblocking algorithm given in the AVC standard is presented. This modification allows the algorithm to finish the filtering of a macroblock to finish twenty clock cycles faster than previous single filter designs. This thesis also presents a hardware architecture of the H.264 deblocking filter to be used in the H.264 decoder. The developed architecture allows the filtering of videos streams using 4:2:2 chroma subsampling and 10-bit pixel precision in real-time. The filter was described in VHDL and synthesized for a Spartan-6 FPGA device. Timing analysis showed that is was capable of filtering a macroblock using 4:2:0 chroma subsampling in 124 clock cycles and 4:2:2 chroma subsampling streams in 162 clock cycles. The filter can also provide real-time deblocking of HDTV video (1920x1080) of up to 988 frames per second.

In this dissertation we deal with methods of minimizing block artefacts in digital terrestrial TV broadcasting. These artefacts are caused by compressions based on the cosine transformation (JPEG, MPEG2 I-Frames). The aim of this work is therefore to create a DVB-J application the main function of which would be to minimize block artefacts in natural images transmitted by DVB-T. That is why we first inquire into the technology of DVB digital transmission and MHP platform which provides the function and the running of interactive applications. Next, we define differences between Java and JavaTV languages and describe the way they develop, simulate and start DVB-J applications. In the following part of this work, we analyze methods that can be used to detect and minimize block artefacts. Further on, we describe the design of an adaptive filter which minimizes block artefacts (hereinafter just ´MHP-MBA´). The major result of the entire work is an MHP-Deblocking application that in itself implements a newly created MHP-MBA deblocking filter as well as a filter from video kodek H.263. In the final part we concern ourselves with testing this application on a genuine set-top-box in DVB-T broadcasting.

Video compression techniques are commonly used to meet the increasing demands for the storage and transmission of digital video content. Popular video compression techniques such as MPEG video encoding make use of block-transform coding algorithms which are susceptible to blocking artifacts. These artifacts can be reduced using a deblocking process, of which there are many. However, those deblocking algorithms which provide noticeable improvements in visual quality also tend to be computationally expensive and unsuitable for real-time video use. This dissertation selects and examines an appropriate algorithm for real-time video deblocking applications, and describes its hardware implementation on a Altera Cyclone II FPGA. The chosen algorithm is based on the concept of shifted thresholding; it reduces computational complexity by several means, such as by using only integer arithmetic and by replacing division operations with bit shifting. The implementation leverages the reduced hardware complexity of the chosen algorithm to cost-effectively implement real-time video deblocking.

Video compression techniques are commonly used to meet the increasing demands for the storage and transmission of digital video content. Popular video compression techniques such as MPEG video encoding make use of block-transform coding algorithms which are susceptible to blocking artifacts. These artifacts can be reduced using a deblocking process, of which there are many. However, those deblocking algorithms which provide noticeable improvements in visual quality also tend to be computationally expensive and unsuitable for real-time video use. This dissertation selects and examines an appropriate algorithm for real-time video deblocking applications, and describes its hardware implementation on a Altera Cyclone II FPGA. The chosen algorithm is based on the concept of shifted thresholding; it reduces computational complexity by several means, such as by using only integer arithmetic and by replacing division operations with bit shifting. The implementation leverages the reduced hardware complexity of the chosen algorithm to cost-effectively implement real-time video deblocking.

Αντικείμενο της παρούσας διπλωματικής εργασίας είναι η παρουσίαση και η μελέτη ενος εναλλακτικού σχεδιασμού του deblocking φίλτρου του προτύπου κωδικοποίησης βίντεο Η.264. Αρχικά επεξηγείται αναλυτικά ο τρόπος λειτουργίας του φίλτρου και στη συνέχεια προτείνεται ένας πρωτοποριακός σχεδιασμός με χρήση pipeline πέντε σταδίων. Ο σχεδιασμός παρουσιάζει σημαντικά πλεονεκτήματα στον τομέα της ταχύτητας (ενδεικτικά εμφανίζεται βελτιωμένη απόδοση στην συχνότητα λειτουργίας και στο throughput). Αυτό πιστοποιήθηκε από μετρήσεις που έγιναν σε συγκεκριμένα fpga και επαλήθευσαν τα θεωρητικά συμπεράσματα που είχαν εξαχθεί. / The standard H.264 (or else MPEG-4 part 10) is nowadays the most widely used standard in the area of video coding as it is supported by the largest enterprises in the internet (including Google, Apple and Youtube). Its most important advantage over the previous standards is that it achieves better bitrate without falling in terms of quality. A crucial part of the standard is the deblocking filter which is applied in each macroblock of a frame so that it reduces the blocking distortion. The filter accounts for about one third of the computational requirements of the standard, something which makes it a really important part of the filtering process. The current diploma thesis presents an alternative design of the filter which achieves better performance than the existing ones. The design is based in the use of two filters (instead of one used in current technology) and moreover, in the application of a pipelined design in each filter. By using a double filter, exploitation of the independence which exists in many parts of the macroblock is achieved. That is to say, it is feasible that different parts of it can be filtered at the same time without facing any problems. Furthermore, the use of the pipeline technique importantly increases the throughput. Needless to say, in order for the desired result to be achieved, the design has to be made really carefully so that the restrictions imposed by the standard will not be failed. The use of this alternative filter design will result in an important raise in the performance. Amongst all, the operating frequency, the throughput and the quality of the produced video will all appear to be considerably risen. It also needs to be mentioned that the inevitable increase of the area used (because of the fact that two filters are used instead of one) is not really important in terms of cost. The structure of the thesis is described in this paragraph. In chapter 1 there is a rather synoptic description of the H.264 standard and the exact position of the deblocking filter in the whole design is clarified. After that, the algorithmic description of the filter follows (Chapter 2). In this chapter, all the parameters participating in the filter are presented in full detail as well as the equations used during the process. In the next chapter (chapter 3), the architecture chosen for the design is presented. That is to say, the block diagram is presented and explained, as well as the table of timings which explains completely how the filter works. The pipelining technique applied in the filter is also analyzed and justified in this chapter. In the next chapter (chapter 4), every structural unit used in the current architecture is analyzed completely and its role in the whole structure is presented. Finally, in chapter 5, the results of the measurements made in typical fpgas of Altera and Xilinx are presented. The results are shown in table format whereas for specific parameters diagrams were used so that the improved performance of the current design compared to the older ones that are widely used, becomes evident.

For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-¢º processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.

Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real. / New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.

Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real. / New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.