The first topic of this thesis is a cell-based design solution of 4¡Ñ8 scanning decoder using RC5 protocol for DECT handsets. It is a keypad scanner ASIC without any embedded microprocessor nor internal ROMs. The keypad scanner uses RC5 transfer protocol which is compatible with remote control and wireless handsets. The keypad scanner built in the handsets must meet the requirement of low power consumption and small die size to avoid shortening the battery lift and increasing chip cost. The proposed ASIC design possesses both of the required advantages. The second topic is a high-performance SRAM using current sense amplifier. Current sensing in SRAMs is very promising method to achieve high speed operations in low-voltage applications. This topic present a current sense amplifier circuit as well as its simulation results.

A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.

Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data. A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4£c-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost. The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power. Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

Convolutinal coding is a coding scheme often employed in deep space communications and recently in digital wireless communications. Viterbi decoders are used to decode convolutional codes. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications. In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment. We considered two methods, clock-gating and toggle-filtering, in our design. A Viterbi decoder consists of five blocks. The clock-gating was applied to the survivor path storage block and the toggle-filtering to the trace-back block of a Viterbi decoder. We followed the standard cell design approach to implement the design. The behavior of a Viterbi decoder was described in VHDL, and then the VHDL description was modified to embed the low-power design. A gate level circuit was obtained from the behavioral description through logic synthesis, and a full scan design was incorporated into the gate level circuit to ease testing. The gate level circuit was placed and routed to generate a layout of the design. Our experimental result shows the proposed design reduces the power dissipation of a Viterbi decoder by about 42 percent compared with the on without considering the low-power design. / Master of Science

In this thesis, the low-power design of two popular error-control code decoders has been presented. It first proposes a low-power Viterbi decoder based on the improved reference path generation method which can lead to significant reduction of the memory accesses during the trace-back operation of the survival memory unit. The use of the reference path has been addressed in the past; this mechanism is further extended in this thesis to take into account the selection of starting states for the trace-back and path prediction operations. Our simulation results show that the best saving ratio of memory access can be up to 92% by choosing the state with the minimum state-metric for both trace-back and path prediction. However, the implementation of our look-ahead path prediction initiated from the minimum state will suffer a lot of area overhead especially for Viterbi applications with large state number. Therefore, this thesis instead realizes a 64-state Viterbi decoder whose path prediction starts from the predicted state obtained from the previous prediction phase. Our implementation results show that the actual power reduction ratio ranges from 31% to 47% for various signal-to-noise ratio settings while the area overhead is about 10%. The second major contribution of this thesis is to apply the similar low-power technique to the design of Soft-Output-Viterbi-Algorithm (SOVA) based Turbo code decoders. Our experimental results show that for eight-state SOVA Turbo code, our reference path generation mechanism can reduce more that 95% memory accesses, which can help saving the overall power consumption by 15.6% with a slight area overhead of 3%.

With the approach of the era of digital TV system around the world, how to grasp the design techniques of the receiver of the DVB-T has become a very important topic. The goal of this thesis is to pursue a highly optimized VLSI architecture compatible to the channel decoding standard of the DVB-T protocol. The channel decoding scheme adopted in DVB-T is based on the concatenated code; which is comprised of an inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules. These modules all require a significant amount of data storage space, therefore the main feature of the proposed channel decoder architectures is to realize the data storage based on RAM instead of registers. This approach can lead to the reduction of silicon area and the dynamic power dissipation compared with the shift register based architecture. In order to achieve this, in the design of Viterbi module, the popular register-exchange and trace-back techniques used for the detection of the survivor path has been combined for the survivor memory management unit. As for the design of Reed-Solomon decoder, it is designed based on the modified inverse-free Berlekamp-Massey algorithm. A novel finite field constant multiplier architecture has been proposed which can reduce the required gate count of the multipliers by 20%. For outer convolutional deinterleaver, a specific address generator has been designed such that the data deinterleaver path can be merged and implemented as two memory blocks. For inner symbol deinterleaver, a lookahead technique has been applied to the design of address generator and deinterleaver memory has been reduced by a half compared with those in the literature. These four modules have been verified and integrated as robust channel decoder silicon IP. The related models used for IP integration and verification have also been provided. The prototyping on the FPGA has been tested to satisfy the requirement of the spec.

Chess is a deep and intricate game, the master of which depends on learning tens of thousands of the patterns that may occur on the board. At Noctie, their mission is to aid this learning process through humanlike chess AI. A prominent challenge lies in curating instructive chess positions for students. Usually these are either manually found by going through large numbers of real games, or handcrafted – a time-consuming process. For effective learning, it is often useful to collect many positions following the same theme, or exhibiting the same type of pattern. Curating such collections from real games is a challenging task. This thesis investigates the transformer decoder-only architecture and its capability of generating realistic, game-like chess-positions. This investigation involved the development and training of a decoder model using Pytorch, and a simple web-based Turing test gaining larger understanding of testers experience. The developed chess model successfully generates chess positions, with constraining possibilities of fixed pieces, score intervals, and fixed empty positions. Controlled re-generation ensures satisfaction of score intervals, while empty positions are handled by iterating over the model's probabilities. Based on the limited data provided by the Turing test, the model seems to fool players below 2000 rank-points on chess.com, where guess percentages land near the 50 percent mark, providing no clear indication that it deviates from randomness.

No description available.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper describes the recently developed Loral Instrumentation ground-based equipment used to select and process post-flight test data from the Boeing 777 airplane as it is played back from a digital tape recorder (e.g., the Ampex DCRSi II) at very high speeds. Gigabytes (GB) of data, stored on recorder cassettes in the Boeing 777 during flight testing, are played back on the ground at a 15-30 MB/sec rate into ten multiplexed Loral Instrumentation System 500 Model 550s for high-speed decoding, processing, time correlation, and subsequent storage or distribution. The ten Loral 550s are multiplexed for independent data path processing from ten separate tape sources simultaneously. This system features a parallel multiplexed configuration that allows Boeing to perform critical 777 flight test processing at unprecedented speeds. Boeing calls this system the Parallel Multiplexed Processing Data (PMPD) System. The key advantage of the ground station's design is that Boeing engineers can add their own application-specific control and setup software. The Loral 550 VMEbus allows Boeing to add VME modules when needed, ensuring system growth with the addition of other LI-developed products, Boeing-developed products or purchased VME modules. With hundreds of third-party VME modules available, system expansion is unlimited. The final system has the capability to input data at 15 MB/sec. The present aggregate throughput capability of all ten 24-bit Decoders is 150 MB/sec from ten separate tape sources. A 24-bit Decoder was designed to support the 30 MB/sec DCRSi III so that the system can eventually support a total aggregate throughput of 300 MB/sec. Clearly, such high data selection, rejection, and processing will significantly accelerate flight certification and production testing of today's state-of-the-art aircraft. This system was supplied with low level software interfaces such that the customer would develop their own applications specific code and displays. The Loral 550 lends itself to this kind of applications due to its VME chassis, VxWorks operating system and the modularity of the software.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / In the event of a NASA Space Shuttle mission landing at the While Sands Missile Range, White Sands, New Mexico, a data communications system for processing Shuttle’s telemetry data has been installed there in the Master Control Telemetry Station, JIG-56. This data system required a Viterbi decoder since the Shuttle’s data is convolutionally encoded. However, the Shuttle uses a nonstandard code, and the manufacturer which in the past has provided decoders for Shuttle support, no longer produces them. Since no other company produced a Viterbi decoder designed to decode the shuttle’s data, it was necessary to develop the required decoder. The purpose of this paper is to describe the functional performance requirements and design of this decoder.