Anycast is a new communication service defined in IPv6 (Internet Protocol Version 6) [6]. An anycast message is the one that should be delivered to the 'nearest' member in a group of designated recipients. The ¡¥nearest¡¦ is not always the ¡¥best¡¦ member. In this paper, we propose a routing protocol for anycast message. It is composed of two subprotocols: the routing table establishment subprotocol and the packet forwarding subprotocol. In the routing table establishment subprotocol, we propose a mininum delay path method (MDP). We get a minimum delay path from router to destination by MDP. In the packet forwarding protocol, we propose a minimum delay and load balancing method (MDLB). We dispatch traffic load to a server with minimum delay and light load by MDLB. The performance has demonstrated the benefits of MDP and MDLB in reducing end-to-end delay and increasing throughput of network.

OFDM-based WLAN systems are originally used for nearly static environment. But in the trend of user-convenience, if we want to support mobility, the most important issue is the Doppler effect caused by the object velocity. We investigate how the Doppler effect, signal-to-noise ratio (SNR) and imperfect estimation of channel impulse response (CIR) and the maximum Doppler shift fd influence the final bit error rate (BER) under the simulation environment, modified WLAN 802.11a specification. For these effects, we give some simulation results and conclusions. If CIR and df are known with the same number of multipath, we can see some phenomenon. First, the BER is dominated by AWGN noise. Second, under the same channel delay spread, the higher the object velocity is, the more serious the BER is. Third, under the same the object velocity, the more serious the BER is. If CIR is known instead of fd, under the same error percentage of fd and the same number of multipath, the lesser the velocity is the lesser the BER curve changes. If fd is known instead of CIR with the same number of multipath, the longer the channel delay spread is, the more serious the BER is.

Sound waves are highly conductive in the ocean; therefore, they are used in underwater detection and signal transmission. During these applications, we may receive some signals, such as radiated noise, self-noise, reverberation noise, target noise, and ambient noise. These signals are influential in the application of underwater acoustics, so many people study underwater noise and create numerous mathematical and physical models in order to improve the applications. According to the past researches, ambient noise is the most complicated one among all the other underwater noise. Until now, there are still some unknown factors in the ambient noise study, many of which are too intricate to be modulated. Accordingly, it is very important to know more about the ambient noise for the enhancing of the quality of underwater communication and detection, which is the reason why people keep researching on ambient noise. Among all kinds of ambient noise, wind-generated noise is not only loud in volume, but also wide in frequency scale, which makes it the most detectable noise during sound detection. In order to understand wind-generated noise, we have compiled past papers first to look for the correlation between physical mechanisms and models of mathematics. In addition, we have constructed a measuring system for underwater sound in the ocean and another measuring system for wind on land. Data from the two measuring system were analyzed by statistics. One of the correlations between wind and ambient noise is that the stronger wind appears, the louder ambient noise is generated. But wind does not always generate ambient noise; it has to be strong enough to generate ambient noise. However, even when the wind is strong enough, ambient noise is not generated immediately, but with a delay. By analyzing the data, we have not only proved the credibility of the data from the old researches, but also presented a method of statistics for analyzing the wind delay effect, and the minimum velocities of wind which generates ambient noise.

Power consumption is gradually becoming an important issue in designing computing systems. Most of the low power researches focused on semiconductor technique and hardware architecture design but less utilized the techniques of software optimization. In this thesis, list scheduling is employed to reduce the energy cost for the Processor-in-Memory system not at the sacrifice of execution performance. In our list-based low power scheduling algorithm, a priority list will be maintained for each scheduling step. The scheduling kernel utilizes the priority of mobility to determine which task will be scheduled to the suitable processor based on the energy cost model of energy-delay product. The experimental results are presented and discussed.

The present research presents procedures for exploitation of level sensitive latches in wire pipelining. The user gives a Steiner tree, having a signal source and set of destination or sinks, and the location in rectangular plane, capacitive load and required arrival time at each of the destinations. The user also defines a library of non-clocked (buffer) elements and clocked elements (flip-flop and latch), also known as synchronous elements. The first procedure performs concurrent repeater and synchronous element insertion in a bottom-up manner to find the minimum latency that may be achieved between the source and the destinations. The second procedure takes additional input (required latency) for each destination, derived from previous procedure, and finds the repeater and synchronous element assignments for all internal nodes of the Steiner tree, which minimize overall area used. These procedures utilize the latency and area advantages of latch based pipelining over flip-flop based pipelining. The second procedure suggests two methods to tackle the challenges that exist in a latch based design. The deferred delay padding technique is introduced, which removes the short path violations for latches with minimal extra cost.

controllers for discrete-time systems and time-delayed systems. By using bilinear transformation and orthogonal transformation, earlier research results obtained in the continuous-time case are extended to discrete-time situation. The complete set of stabilizing PID controllers for the discrete-time systems is thus obtained. Moreover, this set remains to be a union of convex sets when one particular parameter is fixed. Thus a method to design robust and non-fragile digital PID controllers is proposed by following a similar design procedure for the continuous-time systems. In order to find the stabilizing controller set for systems with time-delays, the relationship between the Nyquist Criterion and Pontryagin’s theory is investigated. The conditions under which one can correctly apply the Nyquist Criterion to time-delayed systems are derived. Then, the complete set of stabilizing PID controllers for arbitrary order LTI systems with time-delay up to a given value is obtained. Furthermore, the stability issue of a system with fixed-delay is also studied and a formula which provides complete knowledge of the distribution of the closed-loop poles is presented. Based on this formula, stabilizing P and PI controller sets for the system with fixed-delay can be computed.

Service interchange ramp terminals provide access from the local highway or urban street system to the freeway. In urban areas, the ramp terminals at the arterial road are usually signalized for separation of all high-volume conflicting movements. If right-turn or other movements exiting from the ramp terminals are high, a free right-turn lane, which improves operations for right-turn and through exiting traffic, is sometimes provided at the ramp terminals with an exclusive lane for right-turn vehicles on a departure leg. If the ramp terminal is closely followed by the next downstream intersection, weaving maneuvers will occur since some vehicles make a right turn at the ramp terminal and make a left turn at the downstream intersection. These weaving vehicles usually slow down or stop on the free right-turn lane in order to find an acceptable gap in the arterial road traffic. These slowing or stopping vehicles may cause safety and operational problems. This research evaluates the effect of these weaving maneuvers on the operations of a free right-turn lane at the ramp terminals. To provide a means for evaluating free right-turn lane operations, a linear regression model was developed to predict the delay on the free right-turn lane caused by stopped or slowed vehicles planning on making a weaving maneuver. The variables for this model were arterial through volumes, weaving volumes, number of lanes, and ramp spacing within the interchange. The regression model was based upon the results of the CORSIM traffic simulation model that was calibrated using field data obtained from the study site in College Station, Texas. Once the predicted model was developed, the model validation was performed using the field data to check the accuracy of its prediction. A statistical measure was performed for quantifying the difference between the observed and predicted delay on the free right turn lane. From the research results, it was concluded that the weaving maneuvers influence the operation of a free right-turn lane and cause delay on the free right-turn lane.

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which models delay faults caused by the combination of spot defects and parametric process variation. According to the new model, a realistic delay fault coverage metric has been developed. Traditional path delay fault coverage metrics result in unrealistically low fault coverage, and the real test quality is not reflected. The new metric uses a statistical approach and the simulation based fault coverage is consistent with silicon data. Fast simulation algorithms are also included in this dissertation. The new metric suggests that testing the K longest paths per gate (KLPG) has high detection probability for small delay faults under process variation. In this dissertation, a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate for both combinational and sequential circuits is presented. Many techniques are used to reduce search space and CPU time significantly. Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288. The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches.

Modern digital designs require high performance and low cost. In this scenario, timing analysis is an essential step for each phase of the integrated circuit design cycle. To minimize the design turn-around time, the ability to correctly predict the timing behavior of the chip is extremely important. This has resulted in a demand for techniques to perform an accurate timing analysis. A number of existing timing analysis approaches are available. Most of these are pessimistic in nature due because of some inherent inaccuracies in the modeling of the timing behavior of logic gates. Although some techniques use accurate gate delay models, they have only been used to calculate the longest sensitizable delay or the shortest topological path delay for the circuit. In this work, a procedure to and the shortest destabilizing delay, as well as the longest sensitizable delay of a static CMOS circuit is developed. This procedure is also able to determine the exact circuit path as well as the input vector transition for which the shortest destabilizing (or longest sensitizable) delay can be achieved. Over a number of examples, on an average, the minimum destabilizing delay results in an improvement of 24% as compared to the minimum static timing analysis approach. The maximum sensitizable timing analysis results in an improvement of 7% over sensitizable timing analysis with pin-to-output delays. Therefore, the results show that the pessismism in timing analysis can be considerably decreased by using data dependent gate delays for maximum as well as minimum sensitizable timing analysis.

For any congestion control mechanisms, the most fundamental design objectives are stability and scalability. However, achieving both properties are very challenging in such a heterogeneous environment as the Internet. From the end-users' perspective, heterogeneity is due to the fact that different flows have different routing paths and therefore different communication delays, which can significantly affect stability of the entire system. In this work, we successfully address this problem by first proving a sufficient and necessary condition for a system to be stable under arbitrary delay. Utilizing this result, we design a series of practical congestion control protocols (MKC and JetMax) that achieve stability regardless of delay as well as many additional appealing properties. From the routers' perspective, the system is heterogeneous because the incoming traffic is a mixture of short- and long-lived, TCP and non-TCP flows. This imposes a severe challenge on traditional buffer sizing mechanisms, which are derived using the simplistic model of a single or multiple synchronized long-lived TCP flows. To overcome this problem, we take a control-theoretic approach and design a new intelligent buffer sizing scheme called Adaptive Buffer Sizing (ABS), which based on the current incoming traffic, dynamically sets the optimal buffer size under the target performance constraints. Our extensive simulation results demonstrate that ABS exhibits quick responses to changes of traffic load, scalability to a large number of incoming flows, and robustness to generic Internet traffic.