Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.

Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 124-125).

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 165-169). Also available via the Internet.

Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 79-80). Also available via the Internet.

Report (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 60-62). Also available via the Internet.

Lab-on-a-Chip systems and the associated micro-fabrication technologies have been around for almost three decades. However, the rapidly shifting technological landscape and the multidisciplinary nature of the engineering know-how have made it extremely difficult for a majority of these technologies to materialize to find applications and find commercial products. In order to address this gap, researchers worldwide have attempted to implement design automation paradigms typically used for VLSI engineering and apply them to these Lab-on-a-Chip. However, almost all of these efforts have been disconnected, resulting in a delayed/stalled application of algorithmic advances on real-world device design. FluigiCAD will allow the rapid application and integration of innovative ideas into a single cohesive workflow. / 2024-06-13T00:00:00Z

<p>Two important deficiencies have been identified for the integration of CAD and automated process planning. These deficiencies stem from the lack of a uniform representation scheme of pans and products, and an effective communication for CAD and process planning. This thesis presents a new approach and original knowledge regarding the integration and individual aspects of feature-based design, cellular manufacturing planning, inspection planning and assembly sequence planning.</p> <p>A high-level new language called Feature-based Design Description Language (FDDL) has been proposed and designed with a feature representation scheme. Its syntax, semantics and vocabulary have been defined with consideration given to the user, the engineering terminology, and the computer implementation. The FDDL system consists of a number of lexical analyzers, a parser and three code generators. Once the products or parts modeled by the FDDL, or by a feature-based modeler, are processed using the FDDL system, inputs are created for manufacturing tasks planning systems.</p> <p>A feature-based modeling and manufacturing tasks planning system has been designed and implemented, and consists of a prototype of a feature-based modeler, the FDDL system, a feature-based cellular manufacturing planning system, a feature-based automated inspection task planner, and a prototype assembly sequence planner. The prototype feature-based modeler is used to model components using features. All expert tolerancing consultant module has been included in the modeler to assist the user. Cellular manufacturing planning deals with group formation and parts assignment to cells. A clustering-based optimization approach has been proposed and implemented for the formation of machine cells and part families. A feature-based assignment system has been developed to integrate the feature-based design and the formed cells. Automata and pattern recognition techniques, in combination with manufacturing knowledge, are used in the system. The feature-based inspection planner has been developed to integrate the feature-based design and a Coordinate Measuring Machine (CMM). Original inspection strategies and knowledge have been developed for CMM, based on the analysis of CMM characteristics, tolerancing theories, features representation, part structure and geometry. A knowledge-based approach has been presented to integrate CAD with the assembly sequence planning. A prototype of such an assembly sequence planner has been developed for generating the assembly sequence for products from the design directly.</p> / Doctor of Philosophy (PhD)

This thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. The synthesis system internal format contains data structures for algorithmic, dataflow, as well as structural VHDL constructs. This framework for performing synthesis over a wide range of abstraction levels is the novel feature of this system. Optimizations for register-transfer level (dataflow) models are discussed along with their implementation. The design and implementation of the synthesis library, which contains information about the hardware components available to perform the synthesis, is also discussed. The output of the synthesis system is in the form of two files, an RNL format netlist and a purely structural VHDL netlist. In order to produce the actual hardware layout, the RNL netlist must be input to VPNR, a standard cell place and route system. The structural VHDL may be simulated to verify the synthesis process. Results of mixed level synthesis are provided. / Master of Science

This thesis describes the development of the Hierarchical Behavioral Test Generator (HBTG) for the testing of VHDL behavioral models. HBTG uses the Process Model Graph of the VHDL behavioral model as the base for test generation. Test sets for individual processes of the model are precomputed and stored in the design library. Using this information, HBTG hierarchically constructs a test sequence that tests the functionality of the model. The test sequence generated by HBTG is used for the simulation of the model. Various features present in HBTG and the implementation of the algorithm are discussed. The idea of an effective test sequence for a VHDL behavioral model is proposed. A system is presented to evaluate the quality of the test sequence generated by the algorithm. Test sequences and coverage results are given for several models. Some suggestions for future improvements to the tools are made. The HBTG forms part of a complete CAD system for rapid development and testing of VHDL behavioral models. / Master of Science