Στην παρούσα διπλωματική εργασία ασχοληθήκαμε με την μελέτη, ανάλυση και εξομοίωση του πιο διαδεδομένου αναλογικού κυκλώματος, του Τελεστικού Ενισχυτή. Αρχικά επιχειρήθηκε μια ανάλυση της επιμέρους δομής ενός Τ.Ε, ενώ παράλληλα γίνεται μια παρουσίαση κάποιων βασικών αναλογικών κυκλωμάτων που χρησιμοποιούνται στον σχεδιασμό του. Ακολούθως επεξηγούνται οι βασικές καθώς και οι προηγμένες επιδόσεις και τεχνικά χαρακτηριστικά του Τ.Ε και δίνονται παραδείγματα για την διασαφήνιση των φαινομένων που τις επηρεάζουν καθώς και των τεχνικών βελτίωσής τους. Σε όλες τις εξομοιώσεις χρησιμοποιήθηκαν EDA (Electronic design automation) tools και η όλη προσέγγιση γίνεται με την χρήση της CMOS τεχνολογίας. Τέλος, παρουσιάζονται οι κατευθύνσεις που τείνει να ακολουθεί σήμερα η τεχνολογία των Τ.Ε. καθώς και θέματα που απασχολούν ή και πρόκειται να απασχολήσουν και στο μέλλον τους σχεδιαστές. / In this Diploma Thesis, I studied, analyzed and simulated today’s most widely used analog circuit block, the Operational Amplifier. In the beginning an analysis of the basic OpAmp structure is presented and various analog circuits that are commonly used during the design process of an OpAmp are described. Then, basic as well as more advanced technical characteristics of the OpΑmp are explained and simulation results are presented to illustrate the phenomena and the parameters that affect the performance of the OpAmp. In simulations EDA (Electronic design automation) tools were used and the whole approach was made with the use of CMOS technology. Concluding, technology trends and issues that designers will face in the future are presented.

O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm. / In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.

O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente. / The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.

The ability to innovate and launch customized products that are well matched to customer demands is a competitive factor for many manufacturing companies. Development of highly customized products requires following an engineer-to-order business process to allow the products to be modified or adapted to new customers’ specifications, which brings more value to the customer and profit to the company. Design of a new product variant involves a large amount of repetitive and time consuming tasks but also information handling activities that are sometimes beyond human capabilities. Such work that does not rely so much on creativity can be carried out more efficiently by applying design automation systems. Design automation stands out as an effective means of cutting costs and lead time for a range of well-defined design activities and is mainly considered as a computer-based tool that processes and manipulates the design information. Adaptation and variant design usually concern generating a new variant of a basic design, which has been developed and proved previously, according to new customer’s demands. In order to efficiently generate a new variant, a deep understanding of the previous design is essential. Such understanding can be achieved by access to the design rationale explaining the reasons and justifications behind the design. Maintenance of design automation systems is essential to retain their usefulness over time and adapt them to new circumstances. New circumstances are, for example, introduction of new variants of existing products, changes in design rules in order to meet new standards or legislations, or changes in technology. To maintain a design automation system, updating the design knowledge (e.g. design rules) is required. Use of design rationale will normally become a necessity to allow a better understanding of the knowledge. Consequently, there is a need of principles and methods to enable capture, structure, and access design rationale. In this study, a framework for modeling design knowledge and managing design rationale in order to support maintenance of design automation systems is presented. Managing of design rationale concerns enabling capture, structure, and access to design rationale. In order to evaluate the applicability of the framework, the findings are tested through design automation systems in two case companies. / Impact / Adapt

The report is a degree project for the bachelor's level in Mechanical Engineering atUppsala University. The thesis was carried out at Scienta Omicron AB in Uppsala,Sweden and it is provided a basis determining rules for a vacuum chamberconfigurator that will be used by Scienta Omicron AB.Scienta Omicron AB wants to automate its vacuum chamber design to increasecompany productivity and profitability within this product line. This degree projectdescribes a basis for a configurator that will be used by the company later.This degree project begins by interviewing Scienta Omicron's R&D manager and theDesign Team to understand the company's needs and the reasons behind the desireto change the company's current process. After discussion with the company, aproject plan for the thesis is established to ensure that all parts of the thesis areperformed in time with good quality.The report presents briefly the theory of vacuum technology, especially regardingultra-high vacuum that is used by Scienta Omicron and several methods are used toachieve the project. The report ends with recommendations for Scienta Omicronwith the intention of continuously improving the result of this thesis i.e. implementingthe new process.An intensive study of vacuum chambers manufactured by the company is carried outby reviewing the company's email conversation between the design department andcustomers as well as chamber drawings in order to understand the design conceptand its limitations.As a part of the project, a requirement specification of the thesis has beendetermined and concept generating performed, resulting in two concepts," clashmodels" and" matrix". These enable the design and implementation of a vacuumchamber configurator by an external company specializing in customer productconfiguration.The chosen concept is clash models because it facilitates the implementation of theconfigurator later. A third-party company, Animech, which will implement the rulesdetermined in this thesis when constructing the configurator which will be used bySOAB. The configurator will be a tool that replaces the design team and gives themtime resources to develop new solutions and products.

O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente. / The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.

O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm. / In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.

O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm. / In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.

As the markets’ needs change rapidly, developing a variety of products that meet customers’ diverse needs is a competitive factor for many manufacturing companies. Development of highly customized products requires following an engineer-to-order business process to allow the products to be modified or adapted to new customers’ specifications, which brings more value to the customer and profit to the company. The design of a new product variant involves a large amount of repetitive and time-consuming tasks but also information handling activities that are sometimes beyond human capabilities. Such work that does not rely so much on creativity can be carried out more efficiently by applying design automation systems. Design automation stands out as an effective means of cutting costs and lead time for a range of well-defined design activities and is mainly considered as a computer-based tool that processes and manipulates the design information. Variant design usually concern generating a new variant of a basic design, that has been developed and proved previously, according to new customer’s demands. To efficiently generate a new variant, a deep understanding of the intention and fundamentals of the design is essential and can be achieved through access to design rationale—the explanation of the reasons and justifications behind the design. The maintenance of product families and their corresponding design automation systems is essential to retaining their usefulness over time and adapting them to new circumstances. Examples of new circumstances can include the introduction of new variants of existing products, changes in design rules to meet new standards or legislations, or changes in technology. To maintain a design automation system, updating the design knowledge (e.g. design rules) is required. The use of design rationale will normally become a necessity for allowing a better understanding of the knowledge. Consequently, there is a need for principles and methods that enable the capture and structure of the design rationale and sharing them with the users. This study presents methods and tools for modeling design knowledge and managing design rationale in order to support the utilization and maintenance of design automation systems. Managing design rationale concerns enabling the capturing, structuring, and sharing of design rationale. The results have been evaluated through design automation systems in two case companies. / Att kunna erbjuda kundanpassade produkter har blivit allt viktigare för många tillverkande företag. Utformningen av en ny produktvariant involverar en stor mängd repetitiva och tidskrävande uppgifter men även informationshanteringsaktiviteter som ibland är bortom mänskliga möjligheter. Sådant arbete som inte förlitar sig så mycket på kreativitet kan genomföras mer effektivt genom att använda designautomatiseringssystem. Designautomatisering framstår som ett effektivt sätt att minska kostnader och ledtid för en rad väldefinierade designaktiviteter och betraktas huvudsakligen som ett datorbaserat verktyg som analyserar och syntetiserar designinformationen. Variantdesign handlar vanligtvis om att skapa en ny variant av en grundläggande design, som har utvecklats och bevisats tidigare enligt nya kunders krav. För att effektivt skapa en ny variant är en djup förståelse för designens avsikt och grundläggande uppbyggnad avgörande och kan uppnås genom tillgång till ”design rationale”- förklaringen av skälen och motiveringarna bakom designen. Underhållet av produktfamiljer och deras motsvarande designautomatiseringssystem är viktigt för att behålla användbarheten över tid och anpassa dem till nya omständigheter. Exempel på nya omständigheter kan innefatta införande av nya varianter av befintliga produkter, ändringar av designregler för att uppfylla nya standarder, lagstiftningar eller tekniska ändringar. För att upprätthålla ett designautomatiseringssystem krävs uppdatering av designkunskapen (t ex designregler). Användningen av design rationale kommer normalt att bli en nödvändighet för att ge en bättre förståelse av kunskapen. Följaktligen finns det ett behov av principer och metoder som möjliggör fångande och strukturering av design rationale och dela dem med användarna. Denna studie presenterar metoder och verktyg för modellering av designkunskap och hantering av design rationale för att stödja utnyttjande och underhåll av designautomatiseringssystem. Vid hantering av design rationale gäller det att göra det möjligt att fånga, strukturera och dela med sig av design rationale. Resultaten har utvärderats genom att undersöka effekterna av dem i designautomationssystem i två företag.

abstract: Multi-material fabrication allows for the creation of individual parts composed of several materials with distinct properties, providing opportunities for integrating mechanisms into monolithic components. Components produced in this manner will have material boundaries which may be points of failure. However, the unique capabilities of multi-material fabrication allow for the use of graded material transitions at these boundaries to mitigate the impact of abrupt material property changes. The goal of this work is to identify methods of creating graded material transitions that can improve the ultimate tensile strength of a multi-material component while maintaining other model properties. Particular focus is given towards transitions that can be produced using low cost manufacturing equipment. This work presents a series of methods for creating graded material transitions which include previously established transition types as well as several novel techniques. Test samples of each transition type were produced using additive manufacturing and their performance was measured. It is shown that some types of transitions can increase the ultimate strength of a part, while others may introduce new stress concentrations that reduce performance. This work then presents a method for adjusting the elastic modulus of a component to which graded material transitions have been added to allow the original design properties to be met. / Dissertation/Thesis / Supplementary code from appendices / Masters Thesis Engineering 2020